View TCC76_4146990.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SPECIFICATION TCC76x
32-bit RISC Microprocessor For Digital Media Player
Rev. 0.07 February 23, 2005
Preliminary
DISCLAIMER
All information and data contained in this datasheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this datasheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Telechips, Inc. does not assume responsibility for patent infringements or other rights of third parties that may result from its use. Further, Telechips, Inc. reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Telechips, Inc.
Important Notice
This product may include technology owned by Microsoft Corporation and in this case it cannot be used or distributed without a license from Microsoft Licensing, GP. For customers who use licensed Codec ICs and/or licensed codec firmware of mp3: "Supply of this product does not convey a license nor imply any right to distribute content created with this product in revenue-generating broadcast systems (terrestrial. Satellite, cable and/or other distribution channels), streaming applications(via internet, intranets and/or other networks), other content distribution systems(payaudio or audio-on-demand applications and the like) or on physical media(compact discs, digital versatile discs, semiconductor chips, hard drives, memory cards and the like). An independent license for such use is required. For details, please visit http://mp3licensing.com" For customers who use other firmware of mp3: "Supply of this product does not convey a license under the relevant intellectual property of Thomson and/or Fraunhofer Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final product. An independent license for such use is required. For details, please visit http://mp3licensing.com"
Preliminary
TCC76x
Revision History
Date
2004-05-10 2004-06-07 2004-07-27 2004-08-19 2004-09-10 2004-09-29
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 REVISION HISTORY
Revision Description
0.00 0.01 0.02 0.03 0.04 0.05 Initial release Temporary release for review. * TCC766/TCC767 descriptions added. * TCC763/TCC764 pin description updated. * Added and modified some descriptions for clarification. * Corrected typographical errors. * Operating temperature range increased. * Electrical specification for the NOR Flash and audio CODEC. * Audio CODEC specification updated. * Corrected PW bits of CSCFGx register. * Corrected Block Diagrams for the TCC763/4/6/7 * TCC768 added. * Register level descriptions removed from Section 3. (CPU) * Corrected errors in SDCFG/MCFG register descriptions. * TCC761 pin description corrected (PD[15:0]). * TCC763/4/6/7 pin description - Voltage range for VDDIO corrected. * GPIO - Block diagram and description for pull-up resistor. * Interrupt Controller - Block diagram and wakeup event register description. * Clock Generator - Power Down, IDLE mode and register description modified.
2005-02-03
0.06
2005-02-23
0.07
Preliminary
iii
TCC76x
TABLE OF CONTENTS Contents
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TABLE OF CONTENTS
Revision History.......................................................................................................................................iii TABLE OF CONTENTS...........................................................................................................................iv Contents ...........................................................................................................................................iv Figures.............................................................................................................................................vii Tables ...............................................................................................................................................ix 1 INTRODUCTION ............................................................................................................................... 1-1 1.1 Features .................................................................................................................................. 1-1 1.2 Applications ............................................................................................................................. 1-2 1.3 Block Diagram ......................................................................................................................... 1-3 1.4 Pin Description ........................................................................................................................ 1-7 1.4.1 TCC760 Pin Description .................................................................................................. 1-7 1.4.2 TCC761 Pin Description ................................................................................................ 1-11 1.4.3 TCC763 / TCC764 Pin Description................................................................................ 1-16 1.4.4 TCC766 Pin Description ................................................................................................ 1-20 1.4.5 TCC767 Pin Description ................................................................................................ 1-27 1.4.6 TCC768 Pin Description ................................................................................................ 1-33 1.5 Package................................................................................................................................. 1-37 2 ADDRESS & REGISTER MAP.......................................................................................................... 2-1 2.1 Address Map............................................................................................................................ 2-1 2.2 Register Map ........................................................................................................................... 2-3 3 CPU ................................................................................................................................................... 3-1 3.1 Overview.................................................................................................................................. 3-1 3.2 Functional Description............................................................................................................. 3-2 3.2.1 Operating States ........................................................................................................... 3-2 3.2.2 Memory Formats ...........................................................................................................3-2 3.2.3 Instruction Length.......................................................................................................... 3-2 3.2.4 Data Types .................................................................................................................... 3-2 3.2.5 Operating Modes........................................................................................................... 3-2 3.2.6 Coprocessor CP15........................................................................................................ 3-3 3.2.7 Protection Unit............................................................................................................... 3-3 3.2.8 Caches and Write Buffer ............................................................................................... 3-4 3.3 Clock Modes............................................................................................................................ 3-6 3.3.1 About clocking modes ................................................................................................... 3-6 3.3.2 FastBus mode ............................................................................................................... 3-6 3.3.3 Asynchronous mode...................................................................................................... 3-6 4 DAI & CDIF ........................................................................................................................................ 4-1 4.1 DAI (Digital Audio Interface) .................................................................................................... 4-1 4.2 Register Description - DAI....................................................................................................... 4-4 4.3 CDIF (CD-DSP Interface) ........................................................................................................ 4-7 4.4 Register Description - CDIF .................................................................................................... 4-9 5 INTERRUPT CONTROLLER............................................................................................................. 5-1 5.1 Overview.................................................................................................................................. 5-1 5.2 Register Description ................................................................................................................ 5-2 6 TIMER / COUNTER........................................................................................................................... 6-1 6.1 Overview.................................................................................................................................. 6-1 6.2 Register Description ................................................................................................................ 6-2 7 GPIO PORT ....................................................................................................................................... 7-1 7.1 Overview.................................................................................................................................. 7-1 7.2 Register Description ................................................................................................................ 7-2 8 CLOCK GENERATOR....................................................................................................................... 8-1 8.1 Overview.................................................................................................................................. 8-1 8.1.1 DCO Control.................................................................................................................. 8-2 8.1.2 Power Down Mode........................................................................................................ 8-3 8.1.3 IDLE Mode .................................................................................................................... 8-3 Preliminary iv
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TABLE OF CONTENTS
8.2 Register Description................................................................................................................ 8-4 9 USB CONTROLLER ......................................................................................................................... 9-1 9.1 Overview ................................................................................................................................. 9-1 9.2 Register Description for USB Device Controller ..................................................................... 9-2 9.3 USB Device DMA Operation ................................................................................................. 9-13 9.3.1 OUT Endpoint DMA Operation ................................................................................... 9-13 9.3.2 IN Endpoint DMA Operation ....................................................................................... 9-13 9.4 Register Description for USB Host Controller ....................................................................... 9-14 10 UART/IrDA..................................................................................................................................... 10-1 10.1 Overview ............................................................................................................................. 10-1 10.2 Register Description............................................................................................................ 10-2 11 GSIO PORT................................................................................................................................... 11-1 11.1 Overview ............................................................................................................................. 11-1 11.2 Register Description............................................................................................................ 11-2 12 MISCELLANEOUS PERIPHERALS ............................................................................................. 12-1 12.1 ADC ..................................................................................................................................... 12-1 12.1.1 Overview ................................................................................................................... 12-1 12.1.2 ADC Controller Register Description ........................................................................ 12-2 12.2 Miscellaneous Register Description.................................................................................... 12-4 13 DMA CONTROLLER ..................................................................................................................... 13-1 13.1 Overview ............................................................................................................................. 13-1 13.2 Register Description............................................................................................................ 13-2 14 LCD CONTROLLER...................................................................................................................... 14-1 14.1 Overview ............................................................................................................................. 14-1 14.2 Related Blocks .................................................................................................................... 14-2 14.3 Interrupt configuration ......................................................................................................... 14-3 14.4 STN LCD ............................................................................................................................. 14-4 14.5 TFT LCD.............................................................................................................................. 14-9 14.6 NTSC/PAL interface .......................................................................................................... 14-11 14.7 Register Description.......................................................................................................... 14-14 15 MEMORY CONTROLLER............................................................................................................. 15-1 15.1 Overview ............................................................................................................................. 15-1 15.2 SDRAM Controller............................................................................................................... 15-3 15.3 Miscellaneous Configuration............................................................................................... 15-6 15.4 External Memory Controller ................................................................................................ 15-9 15.5 Internal Memory ................................................................................................................ 15-14 16 ECC (Error Correction Code) ........................................................................................................ 16-1 16.1 Functional Description......................................................................................................... 16-1 16.2 Register Description............................................................................................................ 16-2 17 I2C CONTROLLER ....................................................................................................................... 17-1 17.1 Functional Description......................................................................................................... 17-1 17.2 Related Blocks .................................................................................................................... 17-1 17.3 Register Description............................................................................................................ 17-2 18 CAMERA INTERFACE .................................................................................................................. 18-1 18.1 Overview ............................................................................................................................. 18-1 18.2 Related Blocks .................................................................................................................... 18-2 18.3 Register Description............................................................................................................ 18-5 19 FAST GPIO.................................................................................................................................... 19-1 19.1 Description .......................................................................................................................... 19-1 20 BOOTING PROCEDURE.............................................................................................................. 20-1 20.1 Overview ............................................................................................................................. 20-1 20.2 External ROM Boot without Encryption (BM == 000) ......................................................... 20-2 20.3 USB Boot (BM == x1x)........................................................................................................ 20-3 20.4 I2C or NAND Boot (BM == 001) .......................................................................................... 20-4 20.5 External ROM Boot with Encryption (BM == 100) .............................................................. 20-6 20.6 Development mode (BM == 101)........................................................................................ 20-7 21 JTAG DEBUG INTERFACE .......................................................................................................... 21-1 21.1 Debugging with OPENice32 & AIJI Spider.......................................................................... 21-2 Preliminary v
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TABLE OF CONTENTS
22 USB 2.0 & CARD INTERFACE ..................................................................................................... 22-1 22.1 Overview.............................................................................................................................. 22-1 22.2 Register Description ............................................................................................................ 22-2 22.3 IDE Commands ................................................................................................................... 22-3 22.3.1 Standard Commands ................................................................................................ 22-3 22.3.2 Vendor Commands ................................................................................................... 22-3 23 ELECTRICAL SPECIFICATION ....................................................................................................23-1 23.1 Absolute Maximum Ratings................................................................................................. 23-1 23.2 Recommended Operating Conditions ................................................................................. 23-1 23.3 Electrical Characteristics ..................................................................................................... 23-2 23.4 Absolute Maximum Ratings - NOR Flash........................................................................... 23-3 23.5 Recommended Operating Conditions - NOR Flash ........................................................... 23-3 23.6 Electrical Characteristics - NOR Flash ............................................................................... 23-3 23.7 Absolute Maximum Ratings - Audio CODEC...................................................................... 23-5 23.8 Recommended Operating Conditions - Audio CODEC...................................................... 23-5 23.9 Electrical Characteristics - Audio CODEC........................................................................... 23-5 24 PACKAGE DIMENSIONS.............................................................................................................. 24-1 24.1 TCC760 Package Dimension .............................................................................................. 24-1 24.2 TCC761 Package Dimension .............................................................................................. 24-2 24.2.1 TCC761-E Package Dimension ................................................................................ 24-2 24.2.2 TCC761-Y Package Dimension ................................................................................ 24-3 24.3 TCC763 / TCC764 Package Dimension.............................................................................. 24-4 24.4 TCC766 Package Dimension .............................................................................................. 24-5 24.5 TCC767 Package Dimension .............................................................................................. 24-6 24.6 TCC768 Package Dimension .............................................................................................. 24-7 25 TCC76x vs. TCC72x...................................................................................................................... 25-1 25.1 Feature Comparison............................................................................................................ 25-1 25.2 Pin Comparison ................................................................................................................... 25-1 25.3 Differences in I/O Cell Characteristics................................................................................. 25-3
Preliminary
vi
TCC76x
Figures
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TABLE OF CONTENTS
Figure 1.1 TCC760 Functional Block Diagram............................................................................ 1-3 Figure 1.2 TCC761 Functional Block Diagram............................................................................ 1-3 Figure 1.3 TCC763 Functional Block Diagram............................................................................ 1-4 Figure 1.4 TCC764 Functional Block Diagram............................................................................ 1-4 Figure 1.5 TCC766 Functional Block Diagram............................................................................ 1-5 Figure 1.6 TCC767 Functional Block Diagram............................................................................ 1-5 Figure 1.7 TCC768 Functional Block Diagram............................................................................ 1-6 Figure 1.8 TCC760 Package Diagram (128-TQFP-1414 / Top View) ................................. 1-37 Figure 1.9 TCC761-E Package Diagram (208-LQFP-2828 / Top View) .............................. 1-38 Figure 1.10 TCC761-Y Package Diagram (208-TBGA-1515 / Bottom View) ...................... 1-39 Figure 1.11 TCC763/TCC764 Package Diagram (144-BGA-1010 / Bottom View) ............. 1-40 Figure 1.12 TCC766 Package Diagram (232-FPBGA-1414 / Bottom View) ....................... 1-41 Figure 1.13 TCC767 Package Diagram (225-FPBGA-1313 / Bottom View) ....................... 1-42 Figure 1.14 TCC768 Package Diagram (144-BGA-1010 / Bottom View)............................ 1-43 Figure 3.1 Little-Endian Addresses of Bytes-Words .............................................................. 3-2 Figure 3.2 4KB Cache Architecture in ARM940T .................................................................. 3-4 Figure 3.3 Asynchronous Clocking Mode .............................................................................. 3-6 Figure 3.4 Switching from FCLK to HCLK in asynchronous mode........................................ 3-6 Figure 4.1 DAI Block Diagram ............................................................................................... 4-2 Figure 4.2 DAI Bus Timing Diagram ...................................................................................... 4-3 Figure 4.3 CDIF Block Diagram............................................................................................. 4-7 Figure 4.4 CDIF Bus Timing Diagram.................................................................................... 4-8 Figure 5.1 Interrupt Controller Block Diagram ....................................................................... 5-1 Figure 6.1 Timer Counter Block Diagram .............................................................................. 6-1 Figure 6.2 Timing diagram of timer/counter ........................................................................... 6-4 Figure 6.3 32-bit Counter Block Diagram .............................................................................. 6-7 Figure 7.1 GPIO Block Diagram ............................................................................................ 7-1 Figure 8.1 Clock Generator Block Diagram ........................................................................... 8-1 Figure 8.2 Clock Generator Register Signals ........................................................................ 8-4 Figure 9.1 USB Host Controller Block Diagram................................................................... 9-14 Figure 10.1 UART Block Diagram........................................................................................ 10-1 Figure 10.2 Timing Diagram of UART Transmission ........................................................... 10-2 Figure 11.1 GSIO Block Diagram ........................................................................................ 11-1 Figure 11.2 GSIO operation ................................................................................................. 11-5 Figure 12.1 ADC Controller Block Diagram ......................................................................... 12-1 Figure 12.2 Pull-Up and Drive Strength Control .................................................................. 12-6 Figure 13.1 DMA Controller Block Diagram......................................................................... 13-1 Figure 13.2 Relation between Hop and Burst Transfers (If burst size is 4.) ........................ 13-5 Figure 13.3 The Example Of Various Types of Transfer. ..................................................... 13-6 Figure 13.4 Enabled 2Channel Transfer. ............................................................................. 13-8 Figure 14.1 LCD controller Block Diagram .......................................................................... 14-1 Figure 14.2 PIN mapping ..................................................................................................... 14-1 Figure 14.3 Output Pixel Data Organization(GPIO_A[31:16] = PXDATA[15:0]).................. 14-3 Figure 14.4 STN LCD pixel data organization ..................................................................... 14-5 Figure 14.5 Color STN Pixel Data ....................................................................................... 14-5 Figure 14.6 Dithering operation ........................................................................................... 14-6 Figure 14.7 STN mode timing.............................................................................................. 14-7 Figure 14.8 Monochrome STN LCD(4bits, 1BPP) example ................................................ 14-8 Figure 14.9 TFT LCD pixel data memory organization........................................................ 14-9 Figure 14.10 TFT LCD output pixel data.............................................................................. 14-9 Figure 14.11 TFT LCD(RGB565) example ........................................................................ 14-10 Figure 14.12 TFT mode timing........................................................................................... 14-10 Figure 14.13 NTSC interlace mode timing......................................................................... 14-11 Figure 14.14 PAL interlace mode timing ............................................................................ 14-12 Figure 14.15 Example: NTSC interlace mode timing diagram .......................................... 14-13 Figure 15.1 Memory Controller Block Diagram.................................................................... 15-1 Preliminary vii
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TABLE OF CONTENTS
Figure 15.2 SDRAM Cycle Diagram .................................................................................... 15-5 Figure 15.3 Basic Timing Diagram for External Memories ................................................ 15-11 Figure 16.1 ECC Block Diagram .......................................................................................... 16-1 Figure 17.1 I2C Block Diagram ............................................................................................ 17-1 Figure 18.1 CIF Block Diagram............................................................................................ 18-1 Figure 18.2 Packing Method ................................................................................................ 18-2 Figure 18.3 YCbCr/RGB 4:4:4/4:2:2/4:2:0 Timing Diagram................................................. 18-3 Figure 18.4 RGB 565/555/bayer Timing Diagram................................................................ 18-4 Figure 18.5 CCIR-656 Format Diagram............................................................................... 18-6 Figure 20.1 Reset Sequence ................................................................................................ 20-1 Figure 20.2 USB boot procedure ......................................................................................... 20-3 Figure 20.3 I2C and NAND boot procedure......................................................................... 20-5 Figure 20.4 Allocation of encrypted F/W code ....................................................................... 20-6 Figure 21.1 JTAG Interface Circuit Diagram .......................................................................... 21-1 Figure 21.2 Connection between Host PC and OPENice32 and Target System ................ 21-2 Figure 21.3 Pin Configuration of 20 and 14 pin Connector..................................................... 21-3 Figure 21.4 20-14 Adapter Board .......................................................................................... 21-3 Figure 24.1 TCC760 Package Dimension (128-TQFP-1414).............................................. 24-1 Figure 24.2 TCC761-E Package Dimension (208-LQFP-2828) .......................................... 24-2 Figure 24.3 TCC761-Y Package Dimension (208-TBGA-1515) .......................................... 24-3 Figure 24.4 TCC763 / TCC764 Package Dimension (144-FPBGA-1010)........................... 24-4 Figure 24.5 TCC766 Package Dimension (232-FPBGA-1414) ........................................... 24-5 Figure 24.6 TCC767 Package Dimension (225-FPBGA-1313) ........................................... 24-6 Figure 24.7 TCC768 Package Dimension (144-FPBGA-1010) ........................................... 24-7
Preliminary
viii
TCC76x
Tables
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TABLE OF CONTENTS
Table 1.1 TCC76x Derivatives ............................................................................................... 1-1 Table 1.2 TCC760 Pin Description ........................................................................................... 1-7 Table 1.3 TCC761 Pin Description ......................................................................................... 1-11 Table 1.4 Mapping between TCC761-E and TCC761-Y...................................................... 1-15 Table 1.5 TCC763 / TCC764 Pin Description......................................................................... 1-16 Table 1.6 TCC766 Pin Description ......................................................................................... 1-20 Table 1.7 TCC767 Pin Description ......................................................................................... 1-27 Table 1.8 TCC768 Pin Description ......................................................................................... 1-33 Table 1.9 Pin Comparison - TCC763 vs. TCC768 .............................................................. 1-36 Table 2.1 Address Allocation Map of the TCC76x.................................................................. 2-1 Table 2.2 Address Allocations for Internal Peripherals (Base = 0x80000000)....................... 2-2 Table 2.3 DAI & CDIF Register Map (Base = 0x80000000) .................................................. 2-3 Table 2.4 Interrupt Controller Register Map (Base = 0x80000100) ....................................... 2-3 Table 2.5 Timer/Counter Register Map (Base = 0x80000200) .............................................. 2-4 Table 2.6 GPIO Register Map (Base = 0x80000300) ............................................................ 2-5 Table 2.7 Clock Generator Register Map (Base = 0x80000400)........................................... 2-5 Table 2.8 USB Register Map (Base = 0x80000500).............................................................. 2-6 Table 2.9 USBH Register Map (Base = 0x80000D00) .......................................................... 2-7 Table 2.10 UART/IrDA Register Map (Base = 0x80000600) ................................................. 2-8 Table 2.11 GSIO Register Map (Base = 0x80000700) .......................................................... 2-8 Table 2.12 I2C Register Map (Base Address = 0x80000800) ............................................... 2-8 Table 2.13 ECC Register Map (Base Address = 0x80000900) ............................................. 2-9 Table 2.14 ADC Interface & ETC Register Map (Base = 0x80000A00)................................. 2-9 Table 2.15 CIF Register Map (Base Address = 0x80000B00)............................................. 2-10 Table 2.16 DMA Controller Register Map (Base = 0x80000E00) ........................................ 2-10 Table 2.17 LCD Controller Register Map (Base = 0x80000F00) ......................................... 2-11 Table 2.18 Memory Controller Register Map (Base = 0xF0000000) ................................... 2-12 Table 2.19 NAND flash Register Map (Base = N * 0x10000000) ........................................ 2-12 Table 3.1 CP15 Register Map................................................................................................ 3-3 Table 4.1 DAI Register Map (Base Address = 0x80000000) ................................................. 4-4 Table 4.2 CDIF Register Map (Base Address = 0x80000080)............................................... 4-9 Table 5.1 Interrupt Controller Register Map (Base Address = 0x80000100)......................... 5-2 Table 5.2 Summary of External Interrupt Configuration......................................................... 5-4 Table 5.3 ICFG Usage for WakeUp Event ............................................................................. 5-6 Table 6.1 Timer/Counter Register Map (Base Address = 0x80000200) ................................ 6-2 Table 6.2 TC32 Count Mode .................................................................................................. 6-7 Table 7.1 GPIO Register Map (Base Address = 0x80000300) .............................................. 7-2 Table 8.1 Example of Phase for Several Target Frequencies................................................ 8-2 Table 8.2 Clock Generator Register Map (Base Address = 0x80000400)............................. 8-4 Table 9.1 USB Register Map (Base Address = 0x80000500)................................................ 9-2 Table 9.2 USB Host Register Map (Base Address = 0x80000D00)..................................... 9-15 Table 10.1 UART/IrDA Register Map (Base Address = 0x80000600) ................................. 10-2 Table 11.1 GSIO Register Map (Base Address = 0x80000700) .......................................... 11-2 Table 12.1 ADC Controller Register Map (Base Address = 0x80000A00) .......................... 12-2 Table 12.2 Miscellaneous Register Map (Base Address = 0x80000A00)............................ 12-4 Table 13.1 DMA Controller Register Map (Base Address = 0x80000E00) .......................... 13-2 Table 14.1 LCD Controller Register Map (Base Address = 0x80000F00) ......................... 14-14 Table 15.1 Memory Controller Register Map (Base Address = 0xF0000000) ..................... 15-2 Table 15.2 NAND flash Register Map (Base Address = N * 0x10000000) .......................... 15-2 Table 15.3 Page size of NAND Flash ................................................................................ 15-14 Table 16.1 ECC Register Map (Base Address = 0x80000900) ........................................... 16-2 Table 17.1 I2C Signal Mapping............................................................................................ 17-1 Table 17.2 I2C Register Map (Base Address = 0x80000800) ............................................. 17-2 Table 18.1 CIF Signal Mapping............................................................................................ 18-2 Table 18.2 CIF Register Map (Base Address = 0x80000B00)............................................. 18-5 Table 19.1 Register of Fast GPIO ......................................................................................... 19-1 Preliminary ix
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TABLE OF CONTENTS
Table 19.2 Instruction of CP5 ................................................................................................ 19-1 Table 20.1 Booting Mode of the TCC76x............................................................................... 20-2 Table 20.2 Supported NAND flash types ............................................................................... 20-5 Table 20.3 Region Settings in Development Mode ................................................................ 20-7 Table 22.1 I/O Port Functions and Selection Addresses...................................................... 22-2 Table 22.2 The Relationship of MST[2:0] Pins and Feature Register.................................. 22-2 Table 22.3 Summary of IDE Commands.............................................................................. 22-3 Table 22.4 Vendor Commands............................................................................................. 22-3 Table 23.1 Absolute Maximum Ratings.................................................................................. 23-1 Table 23.2 Recommended Operating Conditions................................................................... 23-1 Table 23.3 Electrical Characteristics ...................................................................................... 23-2 Table 23.4 Absolute Maximum Ratings - NOR Flash............................................................ 23-3 Table 23.5 Recommended Operating Conditions - NOR Flash............................................. 23-3 Table 23.6 Electrical Characteristics - NOR Flash ................................................................ 23-3 Table 23.7 AC Characteristics - NOR Flash ......................................................................... 23-3 Table 23.8 Absolute Maximum Ratings - Audio CODEC ....................................................... 23-5 Table 23.9 Recommended Operating Conditions - Audio CODEC ....................................... 23-5 Table 23.10 Electrical Characteristics - Audio CODEC Digital I/O....................................... 23-5 Table 23.11 Electrical Characteristics - Audio CODEC Analog............................................ 23-6 Table 23.12 Electrical Characteristics - Audio CODEC Power ............................................ 23-6 Table 25.1 Feature Comparison........................................................................................... 25-1 Table 25.2 Power Voltage Range Comparison .................................................................... 25-1 Table 25.3 Pin Comparison - TCC760.................................................................................25-2 Table 25.4 Pin Comparison - TCC761.................................................................................25-2 Table 25.5 Pin Comparison - TCC763/TCC764 Rev. 0....................................................... 25-2 Table 25.6 Pin Comparison - TCC763/TCC764 Rev. 1....................................................... 25-2
Preliminary
x
TCC76x
1 INTRODUCTION
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
The TCC76x is a system LSI for digital media player based on the ARM940T, ARM's proprietary 32-bit RISC CPU core. It can decode and encode MP3 or other types of audio/voice compression/decompression standards by software based architecture. The on-chip USB controller enables the data transmission between a personal computer and storage device such as NAND flash, HDD, CD etc.
Table 1.1 TCC76x Derivatives
Name
TCC760 TCC761 TCC763 TCC764 TCC766 TCC767 TCC768
Package
128-TQFP-1414 208-LQFP-2828 208-TBGA-1515 144-FPBGA-1010 144-FPBGA-1010 232-FPBGA-1414 225-FPBGA-1313 144-FPBGA-1010
Description
Minimal feature set for digital media player TCC760 + LCD Interface + 32bit External Bus TCC760 + 512KB NOR Flash + High performance Audio CODEC TCC760 + 1MB NOR Flash + High performance Audio CODEC TCC760 + 1MB NOR Flash + High performance Audio CODEC + USB2.0 TCC760 + 1MB NOR Flash + USB2.0 TCC760 + 512KB NOR Flash + High performance Audio CODEC + 2MB SDRAM
1.1 Features
* ARM940T CPU core 4KB instruction, 4KB data cache Operating up to 140MHz 4Kbytes of internal boot ROM with various boot procedure (NAND, UART) and security 64K bytes of internal SRAM for general usage On-chip peripherals (TCC760 and TCC761 Core Blocks) External Memory controller for various memories including PROM, NOR & NAND Flash, SRAM, SDRAM, DDR SDRAM (optional), etc. IDE Interface for HDD or external USB 2.0 device USB1.1 Host & device (Full speed) LCD controller supporting STN, TFT type LCD as well as NTSC/PAL interface (TCC761 only) Video input port for CMOS sensor module interface (TCC761 / TCC760 only) ECC generator for SLC and MLC NAND Flash I2S interface for external audio CODEC I2S interface for CD-DSP interface UART/IrDA for serial host interface GSIO for supporting various serial interfaces GPIO for various purposes Support 4 external interrupts I2C compatible serial bus 2-Channel DMA for transferring a bulk of data Four 16bit timer/counters with PWM output and two 20bit timers 32-bit 1Hz counter General purpose 10-bit ADC JTAG interface for code debugging 4 or 8Mbits of NOR Flash (TCC763 ~ TCC768) High performance Audio CODEC (TCC763, TCC764, TCC766 and TCC768) Highly Efficient Headphone Driver Microphone Input
* * *
* *
Preliminary
1-1
TCC76x
* * Volume Control and Mute
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
USB 2.0 Interface (TCC766/TCC767 only) Memory Card Interfaces Cores (TCC766/TCC767 only) Memory Stick (MS) Memory Stick PRO(MSPRO) SecureDigital Card (SD) MultiMedia Card (MMC) Build-in NAND Flash Memory Controller 16Mbits of SDRAM (TCC768 only) 0.18um low power CMOS process 1.5V ~ 1.95V for core, 1.8V ~ 3.6V for I/O port (TCC760 / TCC761 signals)
* * *
1.2 Applications
Portable MP3 player (Flash or CD type) MP3 Juke Box Digital Audio Encoder/Decoder Digital Internet Radio Server Multimedia Storage Device Low cost PDA
Preliminary
1-2
TCC76x
1.3 Block Diagram
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
USB_DP / GPIO_B[26], USB_DN / GPIO_B[27] USBH_DP / GPIO_B[28], USBH_DN / GPIO_B[29]
Boot ROM (4KB) SRAM (64KB)
USB1.1 Host / Device ECC Generation APB Bridge AHB APB
PLL & CLK Generator Timers / Counters Interrupt Controller GSIO
XIN, XOUT XTIN, XTOUT XFILT TCO2 / GPIO_A[11] TCO5 / GPIO_A[8] TCO1 / GPIO_A[7] TCO4 / GPIO_A[4] TCO0 / GPIO_A[3] TCO3 / GPIO_A[0] EXINT[3:0] / GPIO_A[15:12]
DQM[0:1] / XA[21:20] DQS[1:0] / XA[19:18] ND_CLE / XA[17] ND_ALE / SD_nRAS / XA[16] SD_nCAS / XA[15] SD_BA[1:0] / XA[14:13] XA[12:0] XD[15:0] nOE, nWE, nCS[3:0] SD_nCS, SD_CKE SD_CLK ND_nWE IDE_nCS1 READY
Ext. Memory Interface AHB Wrapper ARM940T
GPIO_A[11:0] GPIO_A[15:0] GPIO_B[29:21] GPIO_B[9:7] GPIO_B[5:0] GPIO_D[17:15] UT_TX / GPIO_B[8] UT_RX / GPIO_B[9] GPIO_A[11:10] GPIO_A[9:8] GPIO_D[17:16] ADIN0 ADIN2 ADIN4
AHB Arbiter
GPIO DMA (2-channel)
UART/IrDA
TDI, TMS, TCK nTRST, TDO
JTAG Video Input Interface
GPIO_D[21:15] GPIO_A[3:0]
DAI (I2S) for CODEC & CD-DSP
I2C
ADC
DAO / GPIO_B[24] MCLK / GPIO_B[23] BCLK / GPIO_B[21] LRCKO / GPIO_B[22] DAI / GPIO_B[25]
GPIO_A[3] / CDAI GPIO_A[2] / CLRCK GPIO_A[1] / CBCLK
Figure 1.1 TCC760 Functional Block Diagram
USB_DP / GPIO_B[26], USB_DN / GPIO_B[27] USBH_DP / GPIO_B[28], USBH_DN / GPIO_B[29] XIN, XOUT XTIN, XTOUT XFILT TCO2 / GPIO_A[11] TCO5 / GPIO_A[8] TCO1 / GPIO_A[7] TCO4 / GPIO_A[4] TCO0 / GPIO_A[3] TCO3 / GPIO_A[0] EXINT[3:0] / GPIO_A[15:12]
Boot ROM (4KB) SRAM (64KB)
USB1.1 Host / Device ECC Generation APB Bridge AHB APB
PLL & CLK Generator Timers / Counters Interrupt Controller GSIO
DQM[0:3] / XA[23:20] DQS[1:0] / XA[19:18] ND_CLE / XA[17] ND_ALE / SD_nRAS / XA[16] SD_nCAS / XA[15] SD_BA[1:0] / XA[14:13] XA[12:0] XD[31:0] nOE, nWE, nCS[3:0] SD_nCS, SD_CKE SD_CLK ND_nWE IDE_nCS1 READY
Ext. Memory Interface AHB Wrapper ARM940T JTAG Video Input Interface LCD, NTSC/PAL Interface
AHB Arbiter
GPIO_B[13:10] GPIO_A[11:0] GPIO_A[31:0] GPIO_B[29:0] GPIO_C[15:0] GPIO_D[21:0] UT_TX / GPIO_B[8] UT_RX / GPIO_B[9] GPIO_A[11:10] GPIO_A[9:8] GPIO_D[17:16]
GPIO DMA (2-channel)
TDI, TMS, TCK nTRST, TDO GPIO_D[21:15] GPIO_A[3:0] GPIO_A[31:16] / PD[15:0] GPIO_B20 / ACBIAS GPIO_B19 / PXCLK GPIO_B18 / VSYNC GPIO_B17 / HSYNC
UART/IrDA
DAI (I2S) for CODEC & CD-DSP
I2C
ADC
ADIN[7:0]
DAO / GPIO_B[24] MCLK / GPIO_B[23] BCLK / GPIO_B[21] LRCKO / GPIO_B[22] DAI / GPIO_B[25]
GPIO_A[3] / CDAI GPIO_A[2] / CLRCK GPIO_A[1] / CBCLK
Figure 1.2 TCC761 Functional Block Diagram
Preliminary
1-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
XA[21:0]
XD[15:0]
XA[21:0] Other TCC760 Pins GPIO_B25 GPIO_B22 XD[15:0]
A[17:0]
DQ[15:0] OE# WE#
NOR Flash
4Mbits
CE# nCS[3] FCSN
TCC760
GPIO_B24 GPIO_B23 GPIO_B21 GPIO_A9 GPIO_B25 GPIO_B22 GPIO_A8
nOE nWE nCS[3]
GPIO_B24 GPIO_B23 GPIO_B21 GPIO_A9 GPIO_A8 LHPOUT DACDAT MCLK RHPOUT BCLK SCLK SDIN
nOE nWE
MICBIAS
VMID
MICBIAS
MIC_IN
MICIN
ROUT
LOUT
VMID
ADCDAT
LCH_IN
LLINEIN
ADCDAT
RCH_OUT
Figure 1.3 TCC763 Functional Block Diagram
XA[21:0] XD[15:0]
LCH_OUT
XA[21:0] Other TCC760 Pins GPIO_B25 GPIO_B22 XD[15:0]
TCC760
GPIO_B24 GPIO_B23 GPIO_B21 GPIO_A9 GPIO_B25 GPIO_B22 GPIO_A8
nOE nWE nCS[3]
RCH_IN
LOUT
ROUT
RLINEIN
DACLRC ADCLRC
Audio CODEC
CSB MODE
WMODE
A[18:0]
DQ[15:0] OE# WE#
NOR Flash
8Mbits
CE# nCS[3] FCSN
GPIO_B24 GPIO_B23 GPIO_B21 GPIO_A9 GPIO_A8 LHPOUT DACDAT MCLK RHPOUT BCLK SCLK SDIN
nOE nWE
MICBIAS
VMID
MICBIAS
MIC_IN
MICIN
ROUT
LOUT
VMID
ADCDAT
LCH_IN
LLINEIN
ADCDAT
Figure 1.4 TCC764 Functional Block Diagram
RCH_OUT
LCH_OUT
Preliminary
RCH_IN
LOUT
ROUT
RLINEIN
DACLRC ADCLRC
Audio CODEC
CSB MODE
WMODE
1-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
XA[21:0]
XD[15:0]
U_CF U_nRESET
USB 2.0 D[15:0] Memory Card nCS1 Controller nIOR nCS0
nIOW nCS[0] nCS[2]
A[2:0]
NOR Flash
8Mbits
nCS[0] nCS[2] GPIO pins Other TCC760 Pins GPIO_B25 GPIO_B22 GPIO_B24 GPIO_B23 GPIO_B21 GPIO_A9 GPIO_A8
XA[21:0]
A[18:0]
TCC760
GPIO_B24 GPIO_B23 GPIO_B21 GPIO_A9 GPIO_B25 GPIO_B22 GPIO_A8
XD[15:0] nOE nWE
DQ[15:0] OE# WE# CE# nCS[3] FCSN
nCS[3]
nOE nWE
MCLK
RHPOUT
ADCDAT
DACLRC ADCLRC ADCDAT
DACDAT
BCLK
SCLK SDIN
MICBIAS
LHPOUT
VMID
MICBIAS
MIC_IN
LCH_IN
Figure 1.5 TCC766 Functional Block Diagram
XA[21:0] XD[15:0]
IIDE_INTRQ IIDE_nRESET IIDE_nUSB U_CF U_nRESET IIDE_nCS3 IIDE_nCS1
RCH_OUT
LCH_OUT
nCS1 nCS0
USB 2.0 D[15:0] Memory Card Controller nIOR
nIOW
A[2:0]
NOR Flash
8Mbits
nCS[0] nCS[2]
nCS[0] nCS[2]
XA[21:0]
A[18:0]
GPIO Pins Other TCC760 Pins
TCC760
XD[15:0] nOE nWE
DQ[15:0] OE# WE# CE# nCS[3] nOE nWE FCSN
nCS[3]
Figure 1.6 TCC767 Functional Block Diagram
Preliminary
RCH_IN
LOUT
ROUT
RLINEIN
LLINEIN
MICIN
ROUT
LOUT
VMID
Audio CODEC
CSB MODE
WMODE
1-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
XA[21:0]
XD[15:0]
SDRAM 16Mbits
CLK SD_CLK SD_CKE SD_nCS CKE CS#
A[10:0], BA UDQM LDQM RAS# CAS# DQ[15:0] WE#
NOR Flash
4Mbits
SD_CLK
SD_CKE
SD_nCS
XA[21:0]
A[17:0]
Other TCC760 Pins GPIO_B25 GPIO_B22 GPIO_B24 GPIO_B23 GPIO_B21 GPIO_A9 GPIO_A8
XD[15:0]
DQ[15:0] OE# WE# CE# nCS[3] nOE nWE FCSN
TCC760
GPIO_B24 GPIO_B23 GPIO_B21 GPIO_A9
GPIO_B25 GPIO_B22
nOE nWE
GPIO_A8
nCS[3]
MCLK
RHPOUT
ADCDAT
DACLRC ADCLRC ADCDAT
DACDAT
BCLK
SCLK SDIN
LHPOUT
MICBIAS
VMID
MICBIAS
MIC_IN
LCH_IN
Figure 1.7 TCC768 Functional Block Diagram
RCH_OUT
LCH_OUT
Preliminary
RCH_IN
RLINEIN
LLINEIN
MICIN
VMID
Audio CODEC
CSB MODE
WMODE
1-6
TCC76x
1.4 Pin Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
The status of the following GPIO pins are latched at the rising edge of nRESET and used to determine the system bus width and boot mode. External devices must not drive output levels onto these pins during reset period.
Pin Name GPIO_A[9] / BW[1] GPIO_A[8] / BW[0] GPIO_B[24] / BM[2] GPIO_B[22] / BM[1] Boot Mode Configuration Input Normal GPIO Input Mode GPIO_B[21] / BM[0] State during reset Bus Width Configuration Input State after reset Normal GPIO Input Mode During normal function with DAI enabled GPIO Output Mode for 2-Wire Interface Clock and Data DAO (I2S Digital Audio Output) LRCK (I2S Word Clock Output) BCLK (I2S Bit Clock Output)
Refer to sections "BOOTING PROCEDURE" and "MEMORY CONTROLLER" for detailed description of BW[1:0] and BM[2:0].
In case of the TCC763, TCC764, TCC766 and TCC768, GPIO_B[22:21]/BM[1:0] signals are connected to internal audio CODEC pins which have on-chip pull-down resistor. If external pull-up resistors are required for these pins, 4.7k is recommended. The TCC76x is a CMOS device. Floating level on input signals cause unstable device operation and abnormal current consumption. Pull-up or pull-down resistors should be used appropriately for input or bidirectional pins. Notation I: O: I/O: AI: AO: PWR: GND: Input Output Bidirectional Analog Input Analog Output Power Ground
1.4.1 TCC760 Pin Description Table 1.2 TCC760 Pin Description
Signal Name Shared Signal Pin # Type Description - TCC760
External Memory Interface Pins
SD_CKE SD_CLK GPIO_B[0] GPO 56 44 I/O I/O SDRAM Clock Enable signal. Active high. / GPIO_B[0] SDRAM Clock / GPO. SD_CLK can be used as a general purpose output. Refer to section "MEMORY CONTROLLER". (MCFG register Bit[3] and Bit[1]) SD_nCS XA[21:20] XA[19:18] XA[17] XA[16] XA[15] XA[14] XA[13] XA[12:7] XA[6:0] XD[15:9] XD[8:4] SD_nCLK / GPIO_B[1] DQM[0:1] DQS[1:0] ND_CLE SD_nRAS / ND_ALE SD_nCAS SD_BA[1] SD_BA[0] 46 43:42 40:39 38 37 36 35 34 31:26 23:17 15:9 6:2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Chip select signal for SDRAM, Active low / Inverted SD_CLK for DDR SDRAM / GPIO_B[1] External Bus Address Bit [21:20] / Data I/O Mask 0, 1 External Bus Address Bit [19:18] / DDR SDRAM Data Strobe [1:0] External Bus Address Bit [17] / CLE for NAND Flash External Bus Address Bit [16] / SDRAM RAS signal / ALE for NAND Flash External Bus Address Bit [15] / SDRAM CAS signal External Bus Address Bit [14] / SDRAM Bank Address 1 External Bus Address Bit [13] / SDRAM Bank Address 0. External Bus Address Bits [12:0] External Bus Data Bit [15:0]
Preliminary
1-7
TCC76x
Signal Name
XD[3:0] NCS[3:0] ND_nWE nWE nOE READY ND_nOE[3:0] / GPIO_B[5:2] GPIO_B[7]
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
Pin #
128:125 50:47 57 58 59 73
Type Description - TCC760
External Bus Chip Select [3:0] / NAND Flash Output Enable [3:0] / GPIO_B[5:2] NAND flash WE. Active low. / GPIO_B[7] Static Memory Write Enable signal. Active low. Static Memory Output Enable signal. Active low. Ready information from external device.
I/O I/O I/O I/O I
USB/UART/IrDA Interface Pins
USB_DP USB_DN USBH_DP USBH_DN UT_TX UT_RX GPIO_B[26] GPIO_B[27] GPIO_B[28] GPIO_B[29] GPIO_B[8] / SD_nCS GPIO_B[9] / IDE_nCS1 51 52 53 54 60 61 I/O I/O I/O I/O I/O I/O USB Function D+ signal / GPIO_B[26] USB Function D- signal / GPIO_B[27] USB Host D+ signal / GPIO_B[28] USB Host D- signal / GPIO_B[29] UART or IrDA TX data / GPIO_B[8] / DDR SDRAM Chip Select UART or IrDA RX data / GPIO_B[9] / IDE Chip Select 1
Audio Interface Pins
BCLK LRCK MCLK DAO DAI GPIO_B[21] / BM[0] GPIO_B[22] / BM[1] GPIO_B[23] GPIO_B[24] / BM[2] GPIO_B[25] 62 63 66 67 68 I/O I/O I/O I/O I/O I2S Bit Clock / GPIO_B[21] / Boot Mode Bit 0 I2S Word Clock / GPIO_B[22] / Boot Mode Bit 1 I2S System Clock / GPIO_B[23] I2S Digital Audio data Output / GPIO_B[24] / Boot Mode Bit 2 I2S Digital Audio data Input / GPIO_B[25]
CD DSP Interface Pins
CBCLK CLRCK CDAI GPIO_A[1] GPIO_A[2] GPIO_A[3] 105 106 107 I/O I/O I/O CD Data Bit Clock Input / GPIO_A[1] CD Data Word Clock Input / GPIO_A[2] CD Data Input / GPIO_A[3]
External Interrupt Pins
EXINT[3] EXINT[2:0] GPIO_A[15] 124 I/O I/O External Interrupt Request [3] / GPIO_A[15] External Interrupt Request [2:0] / GPIO_A[14:12] / FGPIO[14:12] GPIO_A[14:12] / FGPIO[14:12] 123:121
Camera Interface Pins
CISHS CISVS CISCLK CISD[7:4] CISD[3:0] GPIO_D[17] GPIO_D[16] GPIO_D[15] GPIO_D[21:18] GPIO_A[3:0] 92 91 90 96:93 107:104 I/O I/O I/O I/O Horizontal Sync. Input / GPIO_D[17] Vertical Sync. Input / GPIO_D[16] Clock Input / GPIO_D[15] Data Input[7:0] / GPIO_D[21:18], GPIO_A[3:0]
General Purpose I/O Pins
GPIO_A[15] GPIO_A[14:12] GPIO_A[11] GPIO_A[10] GPIO_A[9] / BW[1] GPIO_A[8] / BW[0] EXINT[3] EXINT[2:0] / FGPIO[14:12] SDI2 / FGPIO[11] / SCL FRM2 / FGPIO[10] / SDA SCK2 / FGPIO[9] / SCL SDO2 / FGPIO[8] / SDA SDI1 / FGPIO[7] GPIO_A[7:4] FRM1 / FGPIO[6] SCK1 / FGPIO[5] SDO1 / FGPIO[4] SDI0 / CDAI / FGPIO[3] GPIO_A[3:1] FRM0 / CLRCK / FGPIO[2] SCK0 / CBCLK / FGPIO[1] 107:105 I/O 114 113 111 108 GPIO_A[3:1] / General Purpose Serial I/O 0 / CD Interface Signals / Fast GPIO bits 3 ~ 1 I/O GPIO_A[7:4] / General Purpose Serial I/O 1 / Fast GPIO bits 7 ~ 4 118:115 I/O 124 123:121 I/O I/O GPIO_A[15] / External Interrupt 3 GPIO_A[15:12] / External Interrupt 3 ~ 0 / Fast GPIO bits 14 ~ 12 GPIO_A[11:8] / Bus Width bits 1 ~ 0 / General Purpose Serial I/O 2 Fast GPIO bits 11 ~ 8 / I2C signals. The status of BW[1:0] is latched at the rising edge of nRESET and used to determine external bus width. Refer to section "MEMORY CONTROLLER" for BW[1:0] description.
Preliminary
1-8
TCC76x
Signal Name
GPIO_A[0] GPIO_B[29:28] GPIO_B[27:26] GPIO_B[25] GPIO_B[24] / BM[2] GPIO_B[23] GPIO_B[22] / BM[1] GPIO_B[21] / BM[0] GPIO_B[9] GPIO_B[8] GPIO_B[7] GPIO_B[5:2] GPIO_B[1] GPIO_B[0] GPIO_D[21:18] GPIO_D[17] GPIO_D[16] GPIO_D[15]
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
SDO0 / FGPIO[0] USBH_DN, USBH_DP USB_DN, USB_DP DAI DAO MCLK LRCK BCLK UT_RX UT_TX / SD_nCS ND_nWE nCS[3:0] SD_nCS / SD_nCLK SD_CKE FGPIO[14:11] / CISD[7:4] FGPIO[10] / SCL / CISHS FGPIO[9] / SDA / CISVS FGPIO[9] / CISCLK
Pin #
104 54:53 52:51 68 67 66 63 62 61 60 57 50:47 46 56 96:93 92 91 90
Type Description - TCC760
I/O I/O I/O GPIO_A[0] / General purpose serial I/O 0 Serial Data Output FGPIO[0] GPIO_B[29:28] / USBH_DN, USBH_DP GPIO_B[27:26] / USB_DN, USB_DP GPIO_B[25:21] / Boot Mode bits 2 ~ 0 / I2S Interface Signals. The status of BM[2:0] is latched at the rising edge of nRESET and I/O used to determine the system boot mode. Refer to sections "BOOTING PROCEDURE" and "MEMORY CONTROLLER" for detailed description on BM[2:0]. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO_B[9 ] / UART RX Signal GPIO_B[8] / UART TX Signal / DDR SDRAM Chip Select GPIO_B[7] / Write Enable for NAND Flash GPIO_B[5:2] / External Chip Select 3 ~ 0 GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR SDRAM. GPIO_B[0] / SDRAM clock control GPIO_D[21:18] / Fast GPIO bits 14 ~11 / Camera Interface Data Inputs 3 ~ 0. Internal pull-up resistors are enabled at reset. GPIO_D[17] / Fast GPIO bit 10/ I2C SCL / Camera Interface Hsync. GPIO_D[16] / Fast GPIO bit 9 / I2C SDA / Camera Interface Vsync. GPIO_D[15] / Fast GPIO bit 8 / Camera Interface Clock
ADC Input Pins
ADIN_0 ADIN_2 ADIN_4 82 83 84 AI AI AI General purpose multi-channel ADC input 0 General purpose multi-channel ADC input 2 General purpose multi-channel ADC input 4
Clock Pins
XIN 74 I Main Crystal Oscillator Input for PLL. 12MHz Crystal Input must be used if USB Boot Mode is required. XOUT XFILT XTIN XTOUT 75 78 69 70 O AO I O Main Crystal Oscillator Output for PLL PLL filter output Sub Crystal Oscillator Input. 32.768kHz is recommended. Input voltage must not exceed VDD_OSC (1.95V max). Sub Crystal Oscillator Output
voltage must not exceed VDD_OSC (1.95V max).
Mode Control Pins
MODE1 PKG1 nRESET 98 89 72 I I I Mode Setting Input 1. Pull-down for normal operation. Package ID1, Pull-up for normal operation. System Reset. Active low.
JTAG Interface Pins
TDI TMS TCK TDO nTRST 99 100 101 102 103 I I I I/O I JTAG serial data input for ARM940T JTAG test mode select for ARM940T JTAG test clock for ARM940T JTAG serial data output for ARM940T. External pull-up resistor is required to prevent floating during normal operation. JTAG reset signal for ARM940T. Active low.
Power Pins
VDDIO 112 76 33 16 PWR Digital Power for I/O (1.8V ~ 3.3V)
Preliminary
1-9
TCC76x
Signal Name
VDD_USB VDD_OSC VDDI
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
-
Pin #
64 71 119 109 41 24 7
Type Description - TCC760
PWR PWR PWR Power for USB I/O (3.3V) Digital Power for Oscillators (1.8V) Digital Power for Internal Core (1.8V)
VDDI_ADC VDDA_ADC VDDA_PLL VSSIO
-
87 81 77 97 65 45 32 1
PWR PWR PWR GND
Digital Power for ADC (1.8V) Analog Power for ADC (3.3V) Analog & Digital Power for PLL (1.8V) Digital Ground for I/O
VSSI
-
120 110 55 25 8
GND
Digital Ground for Internal
VSSI_ADC VBBA_ADC VSSA_ADC VBBA_PLL VSSA_PLL
-
88 86 85 80 79
GND GND GND GND GND
Digital Ground for ADC Analog Ground for ADC Analog Ground for ADC Analog Ground for PLL Analog Ground for PLL
Preliminary
1-10
TCC76x
1.4.2 TCC761 Pin Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Table 1.3 TCC761 Pin Description
Signal Name
SD_CKE SD_CLK
Shared Signal
GPIO_B[0] GPO
Pin #
95 77
Type Description - TCC761
External Memory Interface Pins
I/O I/O SDRAM Clock Enable signal. Active high. / GPIO_B[0] SDRAM Clock / GPO. SD_CLK can be used as a general purpose output. Refer to section "MEMORY CONTROLLER". (MCFG register Bit[3] and Bit[1]) SD_nCS XA[23:22] XA[21:20] XA[19:18] XA[17] XA[16] XA[15] XA[14] XA[13] XA[12:7] XA[6:0] XD[15:9] XD[8:4] XD[3:0] XD[31:24] XD[23:16] NCS[3:0] IDE_nCS1 ND_nWE nWE nOE READY GPIO_C[15:8] GPIO_C[7:0], ND_nOE[3:0] / GPIO_B[5:2] GPIO_B[6] GPIO_B[7] SD_nCLK / GPIO_B[1] DQM[0:1] DQM[2:3] DQS[1:0] ND_CLE SD_nRAS / ND_ALE SD_nCAS SD_BA[1] SD_BA[0] 80 68:67 66:65 61:60 59 58 57 56 55 50:45 38:32 20:14, 7:3, 208:205 76:69 31:24 84:81 94 96 97 98 118 I/O I/O I/O I/O I/O I/O I External Bus Data Bits [31:16] / GPIO_C[15:0] External Bus Chip Select [3:0] / NAND Flash Output Enable [3:0] / GPIO_B[5:2] IDE chip select 1. Active low. / GPIO_B[6] NAND flash WE. Active low. / GPIO_B[7] Static Memory Write Enable signal. Active low. Static Memory Output Enable signal. Active low. Ready information from external device. I/O External Bus Data Bit [15:0] I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Chip select signal for SDRAM, Active low / Inverted SD_CLK for DDR SDRAM / GPIO_B[1] External Bus Address Bits [23:22] / Data I/O Mask [0:1] External Bus Address Bits [21:20] / Data I/O Mask [2:3] External Bus Address Bit [19:18] / DDR SDRAM Data Strobe [1:0] External Bus Address Bit [17] / CLE for NAND Flash External Bus Address Bit [16] / SDRAM RAS signal / ALE for NAND Flash External Bus Address Bit [15] / SDRAM CAS signal External Bus Address Bit [14] / SDRAM Bank Address 1 External Bus Address Bit [13] / SDRAM Bank Address 0. External Bus Address Bits [12:0]
USB/UART/IrDA Interface Pins
USB_DP USB_DN USBH_DP USBH_DN UT_TX UT_RX GPIO_B[26] GPIO_B[27] GPIO_B[28] GPIO_B[29] GPIO_B[8] / SD_nCS GPIO_B[9] / IDE_nCS1 88 89 90 91 99 100 I/O I/O I/O I/O I/O I/O USB Function D+ signal / GPIO_B[26] USB Function D- signal / GPIO_B[27] USB Host D+ signal / GPIO_B[28] USB Host D- signal / GPIO_B[29] UART or IrDA TX data / GPIO_B[8] / DDR SDRAM Chip Select UART or IrDA RX data / GPIO_B[9] / IDE Chip Select 1
Audio Interface Pins
BCLK LRCK MCLK DAO DAI GPIO_B[21] GPIO_B[22] GPIO_B[23] GPIO_B[24] GPIO_B[25] 101 102 107 108 109 I/O I/O I/O I/O I/O I2S Bit Clock / GPIO_B[21] / Boot Mode Bit 0 I2S Word Clock / GPIO_B[22] / Boot Mode Bit 1 I2S System Clock / GPIO_B[23] I2S Digital Audio data Output / GPIO_B[24] / Boot Mode Bit 2 I2S Digital Audio data Input / GPIO_B[25]
CD DSP Interface Pins
CBCLK GPIO_B[14] 85 I/O CD Data Bit Clock Input / GPIO_B[14]
Preliminary
1-11
TCC76x
Signal Name
CLRCK CDAI
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
GPIO_B[15] GPIO_B[16]
Pin #
86 87
Type Description - TCC761
I/O I/O CD Data Word Clock Input / GPIO_B[15] CD Data input / GPIO_B[16]
External Interrupt Pins
EXINT[3] EXINT[2:0] GPIO_A[15] GPIO_A[14:12]/FGPIO[14:12] 204 203:201 I/O I/O External Interrupt Request [3] / GPIO_A[15] External Interrupt Request [2:0] / GPIO_A[14:12] / FGPIO[14:12]
LCD, NTSC/PAL Interface Pins
HSYNC VSYNC PXCLK AC_BIAS PD[15:12] PD[11:6] PD[5:4] PD[3:0] GPIO_B[17] GPIO_B[18] GPIO_B[19] GPIO_B[20] GPIO_A[31:28] GPIO_A[27:22] GPIO_A[21:20] GPIO_A[19:16] 165 166 167 168 177:174 130:125 122:121 115:112 I/O Pixel data bus [15:0] / GPIO_A[31:16] I/O I/O I/O I/O Line sync / GPIO_B[17] Frame sync / GPIO_B[18] Pixel clock / GPIO_B[19] AC bias control signal / GPIO_B[20]
Camera Interface Pins
CISHS CISVS CISCLK CISD[7:4] CISD[3:0] GPIO_D[17] GPIO_D[16] GPIO_D[15] GPIO_D[21:18] GPIO_A[3:0] 152 151 150 156:153 172:169 I/O I/O I/O I/O Horizontal Sync. Input / GPIO_D[17] Vertical Sync. Input / GPIO_D[16] Clock Input / GPIO_D[15] Data Input[7:0] / GPIO_D[21:18], GPIO_A[3:0]
General Purpose I/O Pins
GPIO_A[31:28] GPIO_A[27:22] GPIO_A[21:20] GPIO_A[19:16] GPIO_A[15] GPIO_A[14:12] GPIO_A[11] GPIO_A[10] GPIO_A[9] / BW[1] GPIO_A[8] / BW[0] PD[15:12] PD[11:6] PD[5:4] PD[3:0] EXINT[3] EXINT[2:0] / FGPIO[14:12] SDI2 / FGPIO[11] / SCL FRM2 / FGPIO[10] / SDA SCK2 / FGPIO[9] / SCL SDO2 / FGPIO[8] / SDA SDI1 / FGPIO[7] GPIO_A[7:4] FRM1 / FGPIO[6] SCK1 / FGPIO[5] SDO1 / FGPIO[4] SDI0 / FGPIO[3] / CISD[3] GPIO_A[3:0] FRM0 / FGPIO[2] / CISD[2] SCK0 / FGPIO[1] / CISD[1] SDO0 / FGPIO[0] / CISD[0] GPIO_B[29:28] GPIO_B[27:26] GPIO_B[25] GPIO_B[24] / BM[2] GPIO_B[23] GPIO_B[22] / BM[1] GPIO_B[21] / BM[0] USBH_DN, USBH_DP USB_DN, USB_DP DAI DAO MCLK LRCK BCLK 91:90 89:88 109 108 107 102 101 I/O I/O I/O GPIO_B[29:28] / USBH_DN, USBH_DP GPIO_B[27:26] / USB_DN, USB_DP GPIO_B[25:21] / Boot Mode bits 2 ~ 0 / I2S Interface Signals. The status of BM[2:0] is latched at the rising edge of nRESET and used to determine the system boot mode. Refer to sections "BOOTING PROCEDURE" and "MEMORY CONTROLLER" for detailed description on BM[2:0]. 172:169 I/O GPIO_A[3:0] / General purpose serial I/O 0 / Fast GPIO bits 3 ~ 0 / Camera Interface Data Inputs 3 ~ 0 186:185 182 178 I/O GPIO_A[7:4] / General Purpose Serial I/O 1 / Fast GPIO bits 7 ~ 4 192:189 I/O 177:174, 130:125 122:121 115:112 204 203:201 I/O I/O GPIO_A[15] / External Interrupt Request 3 GPIO_A[15:12] / External Interrupt Request 3 ~ 0 / Fast GPIO bits 14 ~ 12 GPIO_A[11:8] / Bus Width bits 1 ~ 0 / General Purpose Serial I/O 2 Fast GPIO bits 11 ~ 8 / I2C signals. The status of BW[1:0] is latched at the rising edge of nRESET and used to determine external bus width. Refer to section "MEMORY CONTROLLER" for BW[1:0] description. I/O GPIO_A[31:16] / Pixel Data Bus [15:0]
Preliminary
1-12
TCC76x
Signal Name Shared Signal
ACBIAS GPIO_B[20:17] PXCLK VSYNC HSYNC CDAI GPIO_B[16:14] CLRCK CBCLK SDI13 GPIO_B[13:10] FRM3 SCK3 SDO3 GPIO_B[9] GPIO_B[8] GPIO_B[7] GPIO_B[6] GPIO_B[5:2] GPIO_B[1] GPIO_B[0] GPIO_C[15:0] GPIO_D[14] GPIO_D[13:10] GPIO_D[9:8] GPIO_D[7:6] GPIO_D[5:4] GPIO_D[3:1] GPIO_D[0] GPIO_D[21:18] GPIO_D[17] GPIO_D[16] GPIO_D[15] ADIN[7:0] FGPIO[14:11] / CISD[7:4] FGPIO[10] / SCL / CISHS FGPIO[9] / SDA / CISVS FGPIO[8] / CISCLK UT_RX UT_TX / SD_nCS ND_nWE IDE_nCS1 nCS[3:0] SD_nCS / SD_nCLK SD_CKE XD[31:24] XD[23:16]
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Pin #
168 167 166 165 87 86 85
Type Description - TCC761
I/O
GPIO_B[20:17] / LCD Interface Signals
I/O
GPIO_B[16:14] / CD Interface Signals
11:8
I/O
GPIO_B[13:10] / General Purpose Serial I/O 3
100 99 96 94 84:81 80 95 76:69 31:24 200 196:193 188:187 173, 93 64, 62 44:42 21 156:153 152 151 150 143:136
I/O I/O I/O I/O I/O I/O I/O I/O
GPIO_B[9] / UART RX Signal GPIO_B[8] / UART TX Signal / DDR SDRAM Chip Select. GPIO_B[7] / Write enable for NAND flash GPIO_B[6] / Chip select 1 for IDE Interface GPIO_B[5:2] / External Chip Select 3 ~ 0 GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR SDRAM. GPIO_B[0] / SDRAM clock control GPIO_C[15:0] / External Data Bus [31:16]
I/O
GPIO_D[14:0]
I/O I/O I/O I/O
GPIO_D[21:18] / Fast GPIO bits 14 ~11 / Camera Interface Data Inputs 3 ~ 0. Internal pull-up resistors are enabled at reset. GPIO_D[17] / Fast GPIO bit 10/ I2C SCL / Camera Interface Hsync. GPIO_D[16] / Fast GPIO bit 9 / I2C SDA / Camera Interface Vsync. GPIO_D[15] / Fast GPIO bit 8 / Camera Interface Clock
ADC Input Pins
AI General purpose multi-channel ADC inputs 7 ~ 0
Clock Pins
Main Crystal Oscillator Input for PLL. XIN XOUT XFILT XTIN XTOUT MODE1 PKG1 PKG0 nRESET 119 120 132 110 111 159 149 148 117 I O AO I O I I I I 12MHz Crystal Input must be used if USB Boot Mode is required. Main Crystal Oscillator Output for PLL PLL filter output Sub Crystal Oscillator Input. 32.768kHz is recommended. Input voltage must not exceed VDD_OSC (1.95V max). Sub Crystal Oscillator Output
voltage must not exceed VDD_OSC (1.95V max).
Mode Control Pins
Mode Setting Input 1. Pull-down for normal operation Package ID1. Pull-up for normal operation Package ID0. Pull-down for normal operation System Reset. Active low.
JTAG Interface Pins
TDI TMS 160 161 I I JTAG serial data input for ARM940T JTAG test mode select for ARM940T
Preliminary
1-13
TCC76x
Signal Name
TCK TDO nTRST
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
Pin #
162 163 164
Type Description - TCC761
I I/O I JTAG test clock for ARM940T JTAG serial data output for ARM940T. External pull-up resistor is required to prevent floating during normal operation. JTAG reset signal for ARM940T. Active low.
Power Pins
184 183 124 123 54 53 23 22 104 103 116 198 197 179 63 39 12 146 135 131 158 157 106 105 79 78 52 51 2 1 199 181 180 92 41 40 13 147 145 144 134 133
VDDIO
PWR
Digital Power for I/O (1.8V ~ 3.3V)
VDD_USB VDD_OSC
PWR PWR
Power for USB I/O (3.3V) Digital Power for Oscillators (1.8V)
VDDI
PWR
Digital Power for Internal Core (1.8V)
VDDI_ADC VDDA_ADC VDDA_PLL
PWR PWR PWR
Digital Power for ADC (1.8V) Analog Power for ADC (3.3V) Analog & Digital Power for PLL (1.8V)
VSSIO
GND
Digital Ground for I/O
VSSI
GND
Digital Ground for Internal
VSSI_ADC VBBA_ADC VSSA_ADC VBBA_PLL VSSA_PLL
GND GND GND GND GND
Digital ground for ADC Analog Ground for ADC Analog Ground for ADC Analog Ground for PLL Analog Ground for PLL
Preliminary
1-14
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Table 1.4 Mapping between TCC761-E and TCC761-Y
LQFP TBGA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 A1 C2 D4 B1 C1 D2 D3 E4 D1 E2 E3 F4 E1 F2 F3 G4 F1 G2 G3 H4 G1 H2 H3 J4 H1 J2 J3 K4 J1 K2 K3 L4 K1 L2 L3 M4 L1 M2 M3 N4 M1 N2 N3 N1 P1 P2 P3 R1 T1 R2 R3 T2 Name VSSIO VSSIO XD4 XD5 XD6 XD7 XD8 GPIO_B10 GPIO_B11 GPIO_B12 GPIO_B13 VDDI VSSI XD9 XD10 XD11 XD12 XD13 XD14 XD15 GPIO_D0 VDDIO VDDIO XD16 XD17 XD18 XD19 XD20 XD21 XD22 XD23 XA0 XA1 XA2 XA3 XA4 XA5 XA6 VDDI VSSI VSSI GPIO_D1 GPIO_D2 GPIO_D3 XA7 XA8 XA9 XA10 XA11 XA12 VSSIO VSSIO LQFP TBGA 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 U1 T3 P4 U2 U3 T4 R4 P5 U4 T5 R5 P6 U5 T6 R6 P7 U6 T7 R7 P8 U7 T8 R8 P9 U8 T9 R9 P10 U9 T10 R10 P11 U10 T11 R11 P12 U11 T12 R12 P13 U12 T13 R13 U13 U14 T14 R14 U15 U16 T15 R15 T16 Name VDDIO VDDIO XA13 XA14 XA15 XA16 XA17 XA18 XA19 GPIO_D4 VDDI GPIO_D5 XA20 XA21 XA22 XA23 XD24 XD25 XD26 XD27 XD28 XD29 XD30 XD31 SD_CLK VSSIO VSSIO GPIO_B1 GPIO_B2 GPIO_B3 GPIO_B4 GPIO_B5 GPIO_B14 GPIO_B15 GPIO_B16 USB_DP USB_DN USBH_DP USBH_DN VSSI GPIO_D6 GPIO_B6 GPIO_B0 GPIO_B7 nWE nOE GPIO_B8 GPIO_B9 GPIO_B21 GPIO_B22 VDD_USB VDD_USB LQFP TBGA 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 U17 R16 P14 T17 R17 P16 P15 N14 P17 N16 N15 M14 N17 M16 M15 L14 M17 L16 L15 K14 L17 K16 K15 J14 K17 J16 J15 H14 J17 H16 H15 G14 H17 G16 G15 F14 G17 F16 F15 E14 F17 E16 E15 E17 D17 D16 D15 C17 B17 C16 C15 B16 Name VSSIO VSSIO GPIO_B23 GPIO_B24 GPIO_B25 XTIN XTOUT GPIO_A16 GPIO_A17 GPIO_A18 GPIO_A19 VDDI nRESET MODE0 XIN XOUT GPIO_A20 GPIO_A21 VDDIO VDDIO GPIO_A22 GPIO_A23 GPIO_A24 GPIO_A25 GPIO_A26 GPIO_A27 VDDA_PLL XFILT VSSA_PLL VBBA_PLL VDDA_ADC ADIN_0 ADIN_1 ADIN_2 ADIN_3 ADIN_4 ADIN_5 ADIN_6 ADIN_7 VSSA_ADC VBBA_ADC VDDI_ADC VSSI_ADC PKG0 PKG1 GPIO_D15 GPIO_D16 GPIO_D17 GPIO_D18 GPIO_D19 GPIO_D20 GPIO_D21 LQFP TBGA 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 A17 B15 D14 A16 A15 B14 C14 D13 A14 B13 C13 D12 A13 B12 C12 D11 A12 B11 C11 D10 A11 B10 C10 D9 A10 B9 C9 D8 A9 B8 C8 D7 A8 B7 C7 D6 A7 B6 C6 D5 A6 B5 C5 A5 A4 B4 C4 A3 A2 B3 C3 B2 Name VSSIO VSSIO MODE1 TDI TMS TCK TDO nTRST GPIO_B17 GPIO_B18 GPIO_B19 GPIO_B20 GPIO_A0 GPIO_A1 GPIO_A2 GPIO_A3 GPIO_D7 GPIO_A28 GPIO_A29 GPIO_A30 GPIO_A31 GPIO_A4 VDDI VSSI VSSI GPIO_A5 VDDIO VDDIO GPIO_A6 GPIO_A7 GPIO_D8 GPIO_D9 GPIO_A8 GPIO_A9 GPIO_A10 GPIO_A11 GPIO_D10 GPIO_D11 GPIO_D12 GPIO_D13 VDDI VDDI VSSI GPIO_D14 GPIO_A12 GPIO_A13 GPIO_A14 GPIO_A15 XD0 XD1 XD2 XD3
Preliminary
1-15
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
1.4.3 TCC763 / TCC764 Pin Description Table 1.5 TCC763 / TCC764 Pin Description
Signal Name
SD_CKE SD_CLK
Shared Signal
GPIO_B[0] GPO
Ball
J8 L5
Type Description - TCC763/ TCC764
External Memory Interface Pins
I/O I/O SDRAM Clock Enable signal. Active high. / GPIO_B[0] SDRAM Clock / GPO. SD_CLK can be used as a general purpose output. Refer to section "MEMORY CONTROLLER". (MCFG register Bit[3] and Bit[1]) SD_nCS XA[21:20] XA[19:18] XA[17] XA[16] XA[15] XA[14] XA[13] SD_nCLK / GPIO_B[1] DQM[0:1] DQS[1:0] ND_CLE SD_nRAS / ND_ALE SD_nCAS SD_BA[1] SD_BA[0] L6 L4,K4 K3,L2 L3 G3 M3 M2 M1 J4, K2 M4, J1 H4, H5 XA[12:0] H1, G6 H2, G5 G4, G7 G8 A3, F4 E2, E5 D8, F7 XD[15:0], E1, F6 E3, D4 C2, B1 A7, B2 A10, F8 NCS[3] NCS[2] NCS[1] NCS[0] ND_nWE nWE nOE READY FCSN ND_nOE[3] / GPIO_B[5] ND_nOE[2] / GPIO_B[4] ND_nOE[1] / GPIO_B[3] ND_nOE[0] / GPIO_B[2] GPIO_B[7] H6 J6 K6 J5 L10 M5 H7 J11 A12 I/O I/O I/O I/O I/O I/O I/O I I NAND flash WE. Active low. / GPIO_B[7] Static Memory Write Enable signal. Active low. Static Memory Output Enable signal. Active low. Ready information from external device. NOR Flash Chip Select. Should be connected to nCS[3]. External Bus Chip Select [3:0] / NAND Flash Output Enable [3:0] / GPIO_B[5:2] I/O External Bus Data Bit [15:0] I/O External Bus Address Bits [12:0] I/O I/O I/O I/O I/O I/O I/O I/O Chip select signal for SDRAM, Active low / Inverted SD_CLK for DDR SDRAM / GPIO_B[1] External Bus Address Bit [21:20] / Data I/O Mask 0, 1 External Bus Address Bit [19:18] / DDR SDRAM Data Strobe [1:0] External Bus Address Bit [17] / CLE for NAND Flash External Bus Address Bit [16] / SDRAM RAS signal / ALE for NAND Flash External Bus Address Bit [15] / SDRAM CAS signal External Bus Address Bit [14] / SDRAM Bank Address 1 External Bus Address Bit [13] / SDRAM Bank Address 0.
USB/UART/IrDA Interface Pins
USB_DP USB_DN USBH_DP USBH_DN UT_TX UT_RX GPIO_B[26] GPIO_B[27] GPIO_B[28] GPIO_B[29] GPIO_B[8] / SD_nCS GPIO_B[9] / IDE_nCS1 L7 K8 L8 M9 M10 L9 I/O I/O I/O I/O I/O I/O USB Function D+ signal / GPIO_B[26] USB Function D- signal / GPIO_B[27] USB Host D+ signal / GPIO_B[28] USB Host D- signal / GPIO_B[29] UART or IrDA TX data / GPIO_B[8] / DDR SDRAM Chip Select UART or IrDA RX data / GPIO_B[9] / IDE Chip Select 1
Audio Interface Pins
Preliminary
1-16
TCC76x
Signal Name
BCLK LRCK MCLK DAO DAI ADCDAT LCH_OUT RCH_OUT LOUT ROUT RCH_IN MIC_IN LCH_IN VMID MICBIAS WMODE SDIN SCLK CSB GPIO_A[8] / BW[0] GPIO_A[9] / BW[1]
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
GPIO_B[21] / BM[0] GPIO_B[22] / BM[1] GPIO_B[23] GPIO_B[24] / BM[2] GPIO_B[25]
Ball
J9 L11 K12 K11 K10 H10 E11 E12 B9 A8 F1 A4 F2 B5 D5 F3 D6 E7
Type Description - TCC763/ TCC764
I/O I/O I/O I/O I/O O AO AO AO AO AI AI AI AO AO I I/O I/O I2S Bit Clock / GPIO_B[21] / Boot Mode Bit 0. Internal pull-down resistor is active at power up. I2S Word Clock / GPIO_B[22] / Boot Mode Bit 1 Internal pull-down resistor is active at power up. I2S System Clock / GPIO_B[23] I2S Digital Audio data Output / GPIO_B[24] / Boot Mode Bit 2 I2S Digital Audio data Input / GPIO_B[25] I2S Digital Audio data Output of audio CODEC(ADC). Must be connected externally to GPIO_B25 (DAI) DAC Left Channel Output of audio CODEC DAC Right Channel Output of audio CODEC DAC Left Channel Line Output of audio CODEC DAC Right Channel Line Output of audio CODEC ADC Right Channel Input of audio CODEC Microphone Input of audio CODEC ADC Left Channel Input of internal audio CODEC Mid-rail reference decoupling point Microphone Bias CODEC I/F Control. Pull-down for normal operation. Internal pull-up resistor is active at power up. 2-Wire MCU Data Input for CODEC 2-Wire MCU Clock Input for CODEC
CD DSP Interface Pins
CBCLK CLRCK CDAI GPIO_A[1] GPIO_A[2] GPIO_A[3] D9 E9 E8 I/O I/O I/O CD Data Bit Clock Input / GPIO_A[1] CD Data Word Clock Input / GPIO_A[2] CD Data Input / GPIO_A[3]
External Interrupt Pins
EXINT[3] EXINT[2:0] GPIO_A15 GPIO_A14 / FGPIO[14] GPIO_A13 / FGPIO[13] GPIO_A12 / FGPIO[12] A2 D3 B3 C3 I/O External Interrupt Request [2:0] / GPIO_A[14:12] / FGPIO[14:12] I/O External Interrupt Request [3] / GPIO_A[15]
General Purpose I/O Pins
GPIO_A[15] GPIO_A[14:12] EXINT[3] EXINT[2:0] / FGPIO[14:12] A2 D3 B3 C3 GPIO_A[11:8] / Bus Width bits 1 ~ 0 / General Purpose Serial I/O 2 GPIO_A[11] GPIO_A[10] GPIO_A[9] / BW[1] GPIO_A[8] / BW[0] SDI2 / FGPIO[11] / SCL FRM2 / FGPIO[10] / SDA SCK2 / FGPIO[9] / SCL SDO2 / FGPIO[8] / SDA E4 E6 E7 D6 I/O Fast GPIO bits 11 ~ 8 / I2C signals. The status of BW[1:0] is latched at the rising edge of nRESET and used to determine external bus width. Refer to section "MEMORY CONTROLLER" for BW[1:0] description. GPIO_A[9:8] is internally connected with audio CODEC signals. Refer to Figure 1.3 for more information. SDI1 / FGPIO[7] GPIO_A[7:4] FRM1 / FGPIO[6] SCK1 / FGPIO[5] SDO1 / FGPIO[4] SDI0 / CDAI / FGPIO[3] GPIO_A[3:1] FRM0 / CLRCK / FGPIO[2] SCK0 / CBCLK / FGPIO[1] B6 C6 B7 B8 E8 E9 D9 I/O GPIO_A[3:1] / General Purpose Serial I/O 0 / CD Interface Signals / Fast GPIO bits 3 ~ 1 I/O GPIO_A[7:4] / General Purpose Serial I/O 1 / Fast GPIO bits 7 ~ 4 I/O GPIO_A[15:12] / External Interrupt 3 ~ 0 / Fast GPIO bits 14 ~ 12 I/O GPIO_A[15] / External Interrupt Request 3
Preliminary
1-17
TCC76x
Signal Name
GPIO_A[0] GPIO_B[29:28] GPIO_B[27:26]
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
SDO0 / FGPIO[0] USBH_DN, USBH_DP USB_DN, USB_DP
Ball
C9 M9,L8 K8,L7
Type Description - TCC763/ TCC764
I/O I/O I/O GPIO_A[0] / General purpose serial I/O 0 Serial Data Output FGPIO[0] GPIO_B[29:28] / USBH_DN, USBH_DP GPIO_B[27:26] / USB_DN, USB_DP GPIO_B[25:21] / Boot Mode bits 2 ~ 0 / I2S Interface Signals. The status of BM[2:0] is latched at the rising edge of nRESET and
GPIO_B[25] GPIO_B[24] / BM[2] GPIO_B[23] GPIO_B[22] / BM[1] GPIO_B[21] / BM[0]
DAI DAO MCLK LRCK BCLK
K10 K11 K12 L11 J9 I/O
used to determine the system boot mode. Refer to sections "BOOTING PROCEDURE" and "MEMORY CONTROLLER" for detailed description on BM[2:0]. GPIO_A[24:21] is internally connected with audio CODEC signals. Refer to Figure 1.3 for more information. GPIO_B[22:21] have internal pull-down resistor which is active at power up.
GPIO_B[9] GPIO_B[8] GPIO_B[7] GPIO_B[5:2] GPIO_B[1] GPIO_B[0] GPIO_D[19] GPIO_D[18] GPIO_D[17] GPIO_D[16] GPIO_D[15]
UT_RX UT_TX / SD_nCS ND_nWE nCS[3:0] SD_nCS / SD_nCLK SD_CKE FGPIO[12] FGPIO[11] FGPIO[10] / SCL FGPIO[9] / SDA FGPIO[8]
L9 M10 L10 H6, J6 K6, J5 L6 J8 H12 D2 G2 A9 G1
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
GPIO_B[9 ] / UART RX Signal GPIO_B[8] / UART TX Signal / DDR SDRAM Chip Select GPIO_B[7] / Write Enable for NAND Flash GPIO_B[5:2] / External Chip Select 3 ~ 0 GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR SDRAM. GPIO_B[0] / SDRAM clock control GPIO_D[19] / Fast GPIO bit 12. Internal pull-up resistor is enabled at reset. GPIO_D[18] / Fast GPIO bit 11. Internal pull-up resistor is enabled at reset. GPIO_D[17] / Fast GPIO bit 10 / I2C SCL GPIO_D[16] / Fast GPIO bit 9 / I2C SDA GPIO_D[15] / Fast GPIO bit 8
ADC Input Pins
ADIN_0 ADIN_2 ADIN_4 G10 F10 E10 AI AI AI General purpose multi-channel ADC input 0 General purpose multi-channel ADC input 2 General purpose multi-channel ADC input 4
Clock Pins
Main Crystal Oscillator Input for PLL. XIN XOUT XFILT XTIN XTOUT H8 G9 G12 K9 J10 I O AO I O 12MHz Crystal Input must be used if USB Boot Mode is required. Main Crystal Oscillator Output for PLL PLL filter output Sub Crystal Oscillator Input. 32.768kHz is recommended. Input voltage must not exceed VDD_OSC (1.95V max). Sub Crystal Oscillator Output
voltage must not exceed VDD_OSC (1.95V max).
JTAG Interface Pins
TDI TMS TCK TDO nTRST C11 D11 C10 D10 B10 I I I I/O I JTAG serial data input for ARM940T JTAG test mode select for ARM940T JTAG test clock for ARM940T JTAG serial data output for ARM940T. External pull-up resistor is required to prevent floating during normal operation. JTAG reset signal for ARM940T. Active low.
Mode Control Pins
MODE1 PKG1 B11 J7 I I Mode Setting Input 1. Pull-down for normal operation. Package ID1. Pull-up for normal operation.
Preliminary
1-18
TCC76x
Signal Name
nRESET
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
Ball
J12
Type Description - TCC763/ TCC764
I System Reset. Active low.
Power Pins
VDDIO VDDIO_USB VDD_NOR VDD_OSC F5 L1 H9 D7 M12 A6 M11 C1 H3 J3 C8 C4 D12 F11 H11 F12 M8 M6 A5 A1 K1 K5 L12 B12 A11 M7 D1 J2 K7 C7 B4 F9 C12 G11 C5 PWR PWR PWR PWR Digital Power for I/O (3.3V) Power for USB I/O (3.3V) Digital Power for NOR Flash Digital Power for Oscillators (1.8V)
VDDI
PWR
Digital Power for Internal Core (1.8V)
VDDI_ADC VDDA_ADC VDDA_PLL HPVDD VDDB_WF VDDC_WF AVDD
PWR PWR PWR PWR PWR PWR PWR
Digital Power for ADC (1.8V) Analog Power for ADC (3.3V) Analog & Digital Power for PLL (1.8V) Analog Power for Headphone Amp Digital Buffer Power for CODEC Core Power for CODEC Analog Power for CODEC
VSSIO
GND
Digital Ground for I/O
VSS_NOR VSS_WF
GND GND
Digital Ground for NOR Flash Digital Ground for CODEC
VSSI
GND
Digital Ground for Internal
VSSI_ADC VSSA_ADC VSSA_PLL AGND
GND GND GND GND
Digital ground for ADC Analog Ground for ADC Analog Ground for PLL Analog Ground for CODEC
Preliminary
1-19
TCC76x
1.4.4 TCC766 Pin Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Table 1.6 TCC766 Pin Description
Signal Name
SD_CKE SD_CLK SD_nCS XA[21] XA[20] XA[19] XA[18] XA[17] XA[16] XA[15] XA[14] XA[13] XA[12] XA[11] XA[10] XA[9] XA[8] XA[7] XA[6] XA[5] XA[4] XA[3] XA[2] XA[1] XA[0] XD[15] XD[14] XD[13] XD[12] XD[11] XD[10] XD[9] XD[8] XD[7] XD[6] XD[5] XD[4] XD[3] XD[2] XD[1] XD[0] nCS[3] nCS[2] nCS[1] nCS[0] nWE nOE READY FCSN
Shared Signal
GPIO_B[0] GPO SD_nCLK / GPIO_B[1] DQM[0] DQM[1] DQS[1] DQS[0] SD_nRAS SD_nCAS SD_BA[1] SD_BA[0]
Ball
L9 P8 M8 L7 N7 L6 L5 P7 D5 N4 N2 N3 N5 M1 M5 M3 L2 L4 K3 J4 P14 J2 J3 J5 H4 H5 L3 F2 E1 E9 F3 D1 A2 B1 F5 C2 D3 G5 F10 H16 F11 M9 R7 R8 P6 N8 D12 K13 C14
Type Description - TCC766
External Memory Interface Pins
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I SDRAM Clock Enable signal. Active high. / GPIO_B[0] SDRAM Clock / GPO. SD_CLK can be used as a general purpose output. Refer to section "MEMORY CONTROLLER". (MCFG register Bit[3] and Bit[1]) Chip select signal for SDRAM, Active low / Inverted SD_CLK for DDR SDRAM / GPIO_B[1] External Bus Address Bit [21] / Data I/O Mask 0 External Bus Address Bit [20] / Data I/O Mask 1 External Bus Address Bit [19] / DDR SDRAM Data Strobe [1] External Bus Address Bit [18] / DDR SDRAM Data Strobe [0] External Bus Address Bit [17] External Bus Address Bit [16] / SDRAM RAS signal External Bus Address Bit [15] / SDRAM CAS signal External Bus Address Bit [14] / SDRAM Bank Address 1 External Bus Address Bit [13] / SDRAM Bank Address 0. External Bus Address Bit [12] External Bus Address Bit [11] External Bus Address Bit [10] External Bus Address Bit [9] External Bus Address Bit [8] External Bus Address Bit [7] External Bus Address Bit [6] External Bus Address Bit [5] External Bus Address Bit [4] External Bus Address Bit [3] External Bus Address Bit [2] External Bus Address Bit [1] External Bus Address Bit [0] External Bus Data Bit [15] External Bus Data Bit [14] External Bus Data Bit [13] External Bus Data Bit [12] External Bus Data Bit [11] External Bus Data Bit [10] External Bus Data Bit [9] External Bus Data Bit [8] External Bus Data Bit [7] External Bus Data Bit [6] External Bus Data Bit [5] External Bus Data Bit [4] External Bus Data Bit [3] External Bus Data Bit [2] External Bus Data Bit [1] External Bus Data Bit [0] External Bus Chip Select 3 / GPIO_B[5]. This pin should be connected to FCSN. External Bus Chip Select 2 / GPIO_B[4]. This pin has an internal connection to the USB2.0 module. Do not use for external components. External Bus Chip Select 1 / GPIO_B[3] External Bus Chip Select 0 / GPIO_B[2]. This pin has an internal connection to the USB2.0 module. Do not use for external components. Static Memory Write Enable signal. Active low. Static Memory Output Enable signal. Active low. Ready information from external device. NOR Flash Chip Select. Should be connected to nCS[3].
GPIO_B[5] GPIO_B[4] / TESTCS2 GPIO_B[3] GPIO_B[2] / TESTCS0
Preliminary
1-20
TCC76x
Signal Name
USB_DP USB_DN USBH_DP USBH_DN UT_TX UT_RX
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
GPIO_B[26] GPIO_B[27] GPIO_B[28] GPIO_B[29] GPIO_B[8] / SD_nCS GPIO_B[9]
Ball
P9 T8 R10 N10 M11 N11
Type Description - TCC766
USB/UART/IrDA Interface Pins
I/O I/O I/O I/O I/O I/O USB Function D+ signal / GPIO_B[26] USB Function D- signal / GPIO_B[27] USB Host D+ signal / GPIO_B[28] USB Host D- signal / GPIO_B[29] UART or IrDA TX data / GPIO_B[8] / DDR SDRAM Chip Select UART or IrDA RX data / GPIO_B[9]
Audio Interface Pins
BCLK LRCK MCLK DAO DAI ADCDAT LCH_OUT RCH_OUT LOUT ROUT RCH_IN MIC_IN LCH_IN VMID MICBIAS WMODE SDIN SCLK CBCLK CLRCK CDAI EXINT[3] EXINT[2] EXINT[1] EXINT[0] CSB GPIO_A[8] / BW[0] GPIO_A[9] / BW[1] GPIO_A[1] GPIO_A[2] GPIO_A[3] GPIO_A[15] GPIO_A[14] / FGPIO[14] GPIO_A[13] / FGPIO[13] GPIO_A[12] / FGPIO[12] GPIO_B[21] / BM[0] GPIO_B[22] / BM[1] GPIO_B[23] GPIO_B[24] / BM[2] GPIO_B[25] N12 L14 N6 M14 M13 K14 H15 G15 C10 C8 F1 A3 G4 A4 C6 H1 E7 B4 E11 E10 D9 D4 A1 B2 E6 I/O I/O I/O I/O I/O O AO AO AO AO AI AI AI AO AO I I I I/O I/O I/O I/O I/O I/O I/O I2S Bit Clock / GPIO_B[21] Internal pull-down resistor is active at power up. I2S Word Clock / GPIO_B[22] Internal pull-down resistor is active at power up. I2S System Clock I2S Digital Audio data Output I2S Digital Audio data Input / GPIO_B[25] must be connected externally to ADCDAT I2S digital audio data output of audio CODEC(ADC) must be connected externally to GPIO_B[25] (DAI) DAC Left Channel Output of audio CODEC DAC Right Channel Output of audio CODEC DAC Left Channel Line Output of audio CODEC DAC Right Channel Line Output of audio CODEC ADC Right Channel Input of audio CODEC Microphone Input of audio CODEC ADC Left Channel Input of internal audio CODEC Mid-rail reference decoupling point Microphone Bias CODEC I/F Control. To enable 2-wire serial interface ot the internal CODEC, low level must be maintained. This pin has an internal pull-up resistor. 2-Wire MCU Data Input for CODEC 2-Wire MCU Clock Input for CODEC
CD DSP Interface Pins
CD Data Bit Clock Input / GPIO_A[1] CD Data Word Clock Input / GPIO_A[2] CD Data Input / GPIO_A[3]
External Interrupt Pins
External Interrupt Request [3] / GPIO_A[15] External Interrupt Request [2] / GPIO_A[14] / FGPIO[14] External Interrupt Request [1] / GPIO_A[13] / FGPIO[13] External Interrupt Request [0] / GPIO_A[12] / FGPIO[12]. This pin is internally connected to the USB2.0 module. Do not use for external component.
General Purpose I/O Pins
GPIO_A[15] GPIO_A[14] GPIO_A[13] GPIO_A[12] GPIO_A[11] GPIO_A[10] GPIO_A[9] / BW[1] EXINT[3] EXINT[2] / FGPIO[14] EXINT[1] / FGPIO[13] TESTIRQ SDI2 / FGPIO[11] / SCL FRM2 / FGPIO[10] / SDA SCLK D4 A1 B2 E6 C7 F8 B4 I/O I/O I/O I/O I/O I/O I/O GPIO_A[15] / External Interrupt Request 3 GPIO_A[14] / External Interrupt Request 2 / Fast GPIO bit 14 GPIO_A[13] / External Interrupt Request 1 / Fast GPIO bit 13 GPIO_A[12] / External Interrupt Request 0 / Fast GPIO bit 12. This pin is internally connected to the USB2.0 module. Do not use for external component. GPIO_A[11] / GSIO2 Data In / Fast GPIO bit 11 / I2C Clock. GPIO_A[10] / GSIO2 FRM / Fast GPIO bit 10 / I2C Data Line. GPIO_A[9] / Bus Width bit 1. The status of BW[1:0] is latched at the rising edge of nRESET and used to determine external bus width. Refer to section "MEMORY CONTROLLER" for BW[1:0] description.
Preliminary
1-21
TCC76x
Signal Name
GPIO_A[8] / BW[0] GPIO_A[7] GPIO_A[6] GPIO_A[5] GPIO_A[4] GPIO_A[3] GPIO_A[2] GPIO_A[1] GPIO_A[0] GPIO_B[29] GPIO_B[28] GPIO_B[27] GPIO_B[26] GPIO_B[25]
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
SDIN SDI1 / FGPIO[7] TESTRST TESTUSB SDO1 / FGPIO[4] SDI0 / CDAI / FGPIO[3] FRM0 / CLRCK / FGPIO[2] SCK0 / CBCLK / FGPIO[1] SDO0 / FGPIO[0] USBH_DN USBH_DP USB_DN USB_DP DAI
Ball
E7 B7 A7 F9 B10 D9 E10 E11 M4 N10 R10 T8 P9 M13
Type Description - TCC766
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPIO_A[8] / Bus Width bit 0. The status of BW[1:0] is latched at the rising edge of nRESET and used to determine external bus width. Refer to section "MEMORY CONTROLLER" for BW[1:0] description. GPIO_A[7] / GSIO1 Data In / Fast GPIO bit 7 GPIO_A[6] / Reset for the internal USB2.0 module. Pull-down for normal operation. GPIO_A[5] / Mode Selection for the internal USB2.0 module. Pullup for normal operation. GPIO_A[4] / GSIO1 Data Output / Fast GPIO bit 4 GPIO_A[3] / GSIO0 Data In / CD Interface Data / Fast GPIO bit 3. This pin has an internal pull-up resistor. GPIO_A[2] / GSIO0 FRM / CD Interface LRCK / Fast GPIO bit 2 This pin has an internal pull-up resistor. GPIO_A[1] / GSIO0 Clock / CD Interface BCLK / Fast GPIO bit 1 This pin has an internal pull-up resistor. GPIO_A[0] / GSIO0 Data Out / FGPIO[0] This pin has an internal pull-up resistor. GPIO_B[29] / USBH_DN GPIO_B[28] / USBH_DP GPIO_B[27] / USB_DN GPIO_B[26] / USB_DP GPIO_B[25] / I2S Interface Data In. Should be connected externally to ADCDAT pin. GPIO_B[24] / Boot Mode bit 2 / I2S Interface Data Out. The status of BM[2:0] is latched at the rising edge of nRESET and used to determine the system boot mode. Refer to sections "BOOTING PROCEDURE" and "MEMORY CONTROLLER" for detailed description on BM[2:0]. Refer to "Functional Block Diagram" for more information about internal connectivity. GPIO_B[23] / I2S Interface Master Clock. Refer to "Functional Block Diagram" for more information about internal connectivity. GPIO_B[22] / Boot Mode bit 1 / I2S Interface LRCK. The status of BM[2:0] is latched at the rising edge of nRESET and used to determine the system boot mode. Refer to sections "BOOTING PROCEDURE" and "MEMORY CONTROLLER" for detailed description on BM[2:0]. Internal pull-down resistor is active at power up. GPIO_B[21] / Boot Mode bit 0 / I2S Interface BCLK. The status of BM[2:0] is latched at the rising edge of nRESET and used to determine the system boot mode. Refer to sections "BOOTING PROCEDURE" and "MEMORY CONTROLLER" for detailed description on BM[2:0]. Internal pull-down resistor is active at power up. GPIO_B[9 ] / UART RX Signal GPIO_B[8] / UART TX Signal / DDR SDRAM Chip Select GPIO_B[7] GPIO_B[5] / External Chip Select 3. Should be connected externally to FCSN. GPIO_B[4] / External Chip Select 2. This pin has an internal connection to the USB2.0 module. Do not connect to external components. GPIO_B[3] / External Chip Select 1 GPIO_B[2] / External Chip Select 0. This pin has an internal connection to the USB2.0 module. Do not connect external components. GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR SDRAM. GPIO_B[0] / SDRAM clock control GPIO_D[17] / Fast GPIO bit 10 / I2C SCL
GPIO_B[24] / BM[2]
DAO
M14
I/O
GPIO_B[23]
MCLK
N6
I/O
GPIO_B[22] / BM[1]
LRCK
L14
I/O
GPIO_B[21] / BM[0]
BCLK
N12
I/O
GPIO_B[9] GPIO_B[8] GPIO_B[7] GPIO_B[5] GPIO_B[4] GPIO_B[3] GPIO_B[2] GPIO_B[1] GPIO_B[0] GPIO_D[17]
UT_RX UT_TX / SD_nCS
N11 M11 L10
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
nCS[3] nCS[2] / TESTCS2 nCS[1] nCS[0] / TESTCS0 SD_nCS / SD_nCLK SD_CKE FGPIO[10] / SCL
M9 R7 R8 P6 M8 L9 B16
Preliminary
1-22
TCC76x
Signal Name
GPIO_D[16] GPIO_D[15] ADIN0 ADIN2 ADIN4
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
FGPIO[9] / SDA FGPIO[8]
Ball
C15 D14 H12 G13 G14
Type Description - TCC766
I/O I/O AI AI AI GPIO_D[16] / Fast GPIO bit 9 / I2C SDA GPIO_D[15] / Fast GPIO bit 8
ADC Input Pins
General purpose multi-channel ADC input 0 General purpose multi-channel ADC input 2 General purpose multi-channel ADC input 4
Clock Pins
XIN XOUT XFILT XTIN XTOUT XSCI XSCO TDI TMS TCK TDO nTRST L16 K15 J13 L11 L12 A6 B5 F12 B13 C12 A13 D11 I O AO I O I O I I I I/O I Main Crystal Oscillator Input for PLL. Input voltage must not exceed VDD_OSC (1.95V max). Main Crystal Oscillator Output for PLL PLL filter output Sub Crystal Oscillator Input. 32.768kHz is recommended. Input voltage must not exceed VDD_OSC (1.95V max). Sub Crystal Oscillator Output Crystal Oscillator Input for USB 2.0 Crystal Oscillator Output for USB 2.0
JTAG Interface Pins
JTAG serial data input for ARM940T JTAG test mode select for ARM940T JTAG test clock for ARM940T JTAG serial data output for ARM940T. External pull-up resistor is required to prevent floating during normal operation. JTAG reset signal for ARM940T. Active low.
Mode Control Pins
MODE1 PKG nRESET D13 E13 L8 I I I Mode Setting Input 1. Used for programming internal NOR flash. Pull-down for normal operation. Package ID, Pull-up for normal operation. System Reset. Active low.
USB 2.0 Interface Pins
DMRS DPRS DM DP RREF RPU D2 C1 B3 C4 C5 E3 I/O I/O I/O I/O I I USB 1.1 D- signal. Connect to external series resistor (391%). USB 1.1 D+ signal. Connect to external series resistor (391%). USB 2.0 D- signal. USB 2.0 D+ signal. Connect external reference resistor (12.1k1%) to ground (VSS_U20). Connect external pull-up resistor(1.5k1%) to USB 2.0 analog power (VDDA_U20).
MS & MSPRO Interface Pins
MS_CLK MS_BS MS_D[3] MS_D[2] MS_D[1] MS_D[0] MS_CD MS_PC MMC_CLK MMC_CMD MMC_D[3] MMC_D[2] MMC_D[1] MMC_D[0] MMC_CD MMC_PC P2 P3 P1 P5 R5 R6 T5 L1 A16 A15 C11 B12 A14 B14 T2 P4 O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O MS/MSPRO Serial protocol Clock signal. MS/MSPRO Serial protocol Bus State signal. MS/MSPRO Data Line [3] MS/MSPRO Data Line [2] MS/MSPRO Data Line [1] MS/MSPRO Data Line [0] MS/MSPRO Card Detection Input. MS/MSPRO Power Control signal with internal pull-up.
MMC & SD Interface Pins
MMC/SD Clock MMC/SD Command/Respond. MMC/SD Data Line [3]. MMC/SD Data Line [2]. MMC/SD Data Line [1]. MMC/SD Data Line [0]. MMC/SD Card Detection Input. MMC/SD Power Control signal with internal pull-up.
Preliminary
1-23
TCC76x
Signal Name Shared Signal
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Ball
Type Description - TCC766
Memory Card Configuration Select Bit 2 MST[2:0] Configuration 111 Record in flash memory by AP Only support MMC/SD card Only support MS/MS_Pro/New MS card Support two kinds of card above. And MMC/SD is the first slot in USB mode. 100 Support two kinds of card above. And MS/MS_Pro/New MS card is the first slot in USB mode. Memory Card Configuration Select Bit 1 Memory Card Configuration Select Bit 0 001 010 011
MST[2]
P10
I/O
MST[1] MST[0] ND_D[15] ND_D[14] ND_D[13] ND_D[12] ND_D[11] ND_D[10] ND_D[9] ND_D[8] ND_D[7] ND_D[6] ND_D[5] ND_D[4] ND_D[3] ND_D[2] ND_D[1] ND_D[0] ND_nCE[1] ND_nCE[0] ND_ALE ND_CLE ND_nOE ND_nWE ND_nWP ND_RDY ND_WP_CTL PRTST AGN_nRESET
T9 T10 C16 D15 D16 E16 E15 F15 F14 F16 T16 P15 R15 T14 R14 T15 R13 P13 R3 R2 R11 R12 P11 T11 P12 T12 A12 K1 M15
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O I/O I I/O I/O I/O
Flash Memory Interface Pins
Flash Data Bus Bit 15 Flash Data Bus Bit 14 Flash Data Bus Bit 13 Flash Data Bus Bit 12 Flash Data Bus Bit 11 Flash Data Bus Bit 10 Flash Data Bus Bit 9 Flash Data Bus Bit 8 Flash Data Bus Bit 7 Flash Data Bus Bit 6 Flash Data Bus Bit 5 Flash Data Bus Bit 4 Flash Data Bus Bit 3 Flash Data Bus Bit 2 Flash Data Bus Bit 1 Flash Data Bus Bit 0 Flash Chip Enable 1, Low active. Flash Chip Enable 0, Low active. Flash Address Latch Enable, High active. Flash Command Latch Enable, High active. Flash Read Control signal, Low active. Flash Write Control signal, Low active. Flash Write Protect Control signal, Low active. Flash Ready/Busy signal. Pull-up resistor required. Flash Write Protect Control Enable Input. ND_nWP signal output is enabled when this signal is high. NAND Flash low level format control signal with internal pull-up. Pull-up for normal operation (low level format disabled). Active low reset signal to AGAND Flash.
Miscellaneous Pins
ACT_nSPND ACS_IND U_CF U_nRESET U_nEA U_nTEST TESTCS2 GPIO_B[4] M16 N1 J16 B15 L15 C13 R7 I/O I/O I I I I I/O Power Control Status Output. High indicates power on state (Access Mode), low indicates power off state (Suspend Mode). Flash Memory Access Indicator with internal pull-up. This signal will be blinking when Flash Memory is accessed. Internal IDE Mode Select Signal. For normal operation, connect this signal to GPIO_A[5]. Reset Signal EAMODE Select for Test. Pull-up for normal operation. Test Mode. (active low). Pull-up for normal operation. Chip Select 2 for the internal IDE interface. This signal is internally connected to GPIO_B[4]. Do not connect to external component. Chip Select 1 for the internal IDE interface. This signal is internally connected to GPIO_B[2]. Do not connect to external component.
TESTCS0
GPIO_B[2]
P6
I/O
Preliminary
1-24
TCC76x
Signal Name
TESTIRQ TESTRST TESTUSB TESTIO7 TESTIO6 TESTIO5 TESTIO4 TEST_MWP TEST_AG TEST_SP TESTEASL TESTHOE TESTHWE TESTREG TESTPACK TESTIS16 TESTCE4 TESTCE3 TESTCE2 TESTFAL TESTFCL TESTFRD TESTFWE VDDIO VDDIO VDDIO VDDIO VDDIO_USB VDD_NOR VDD_OSC VDDI VDDI VDDI VDDI VDDI VDDI VDDA_ADC VDDA_PLL HPVDD VDDB_CDC VDDC_CDC AVDD VSSIO VSSIO VSSIO VSSIO VSSIO VSS_NOR VSS_CDC VSSI VSSI VSSI VSSI VSSI VSSI VSSA_ADC VSSA_PLL
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
GPIO_A[12] GPIO_A[6] GPIO_A[5] GPIO_A[3] GPIO_A[2] GPIO_A[1] GPIO_A[0]
Ball
E6 A7 F9 D9 E10 E11 M4 T7 A9 A10 A11 T4 R9 J12 B9 B11 N16 T1 T3 N14 N15 R16 P16 E8 H3 M6 K16 M12 F6 L13 G12 F7 M7 E4 C9 K2 H13 K12 J15 T6 R4 A5 E12 N13 E5 M2 K5 C3 R1 D7 D8 F4 F13 M10 K4 G16 H14
Type Description - TCC766
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O O O O O PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Active high Interrupt Request. This pin is internally connected to the USB2.0 module. Pull-down for normal operation. Active low hardware reset for the internal USB2.0 module. Pulldown for normal operation. IDE / USB Mode Selection signal. Pull-up for normal operation. (1: IDE Mode, 0:USB Mode) Reserved for Chip Test. Internal pull-up active. Reserved for Chip Test. Internal pull-up active. Reserved for Chip Test. Internal pull-up active. Reserved for Chip Test. Internal pull-up active. Reserved for Chip Test. Pull-up for normal operation. Reserved for Chip Test. Pull-down for normal operation. Reserved for Chip Test. Pull-down for normal operation. Reserved for Chip Test. Pull-down for normal operation. Reserved for Chip Test. Pull-down for normal operation. R eserved for Chip Test. Pull-up for normal operation. R eserved for Chip Test. Pull-up for normal operation. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test.
Power Pins
Digital Power for I/O (3.3V) Digital Power for I/O (3.3V) Digital Power for I/O (3.3V) Digital Power for I/O (3.3V) Power for USB I/O (3.3V) Digital Power for NOR Flash. (3.3V) Digital Power for Oscillators (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Analog Power for ADC (3.3V) Analog & Digital Power for PLL (1.8V) Analog Power for Headphone Amp Digital Buffer Power for CODEC Core Power for CODEC Analog Power for CODEC Digital Ground for I/O Digital Ground for I/O Digital Ground for I/O Digital Ground for I/O Digital Ground for I/O Digital Ground for NOR Flash Digital Ground for CODEC Digital Ground for Internal Digital Ground for Internal Digital Ground for Internal Digital Ground for Internal Digital Ground for Internal Digital Ground for Internal Analog Ground for ADC Analog Ground for PLL
Preliminary
1-25
TCC76x
Signal Name
AGND VDDA_U20 VDDA_U20 VDDA_U20 VDD_U20 VDD_U20 VDDI_U20 VO25 VSSA_U20 VSSA_U20 VSSA_U20 VSS_U20 VSS_U20 VSS_U20 VSS_U20
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
Ball
B8 G1 B6 G3 E14 N9 A8 J1 E2 D6 G2 J14 D10 H2 T13
Type Description - TCC766
GND PWR PWR PWR PWR PWR PWR PWRO GND GND GND GND GND GND GND Analog Ground for CODEC
Power Pins for USB 2.0
3.3V Analog Power for USB 2.0 3.3V for USB 2.0 3.3V for USB 2.0 3.3V for USB 2.0 3.3V for USB 2.0 2.5V Power for Internal. Connect to VO25. 2.5V Output. Connect to VDDI_U20. Ground for USB 2.0 Ground for USB 2.0 Ground for USB 2.0 Ground for USB 2.0 Ground for USB 2.0 Ground for USB 2.0 Ground for USB 2.0
Preliminary
1-26
TCC76x
1.4.5 TCC767 Pin Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Table 1.7 TCC767 Pin Description
Signal Name
SD_CKE SD_CLK SD_nCS XA[21] XA[20] XA[19] XA[18] XA[17] XA[16] XA[15] XA[14] XA[13] XA[12] XA[11] XA[10] XA[9] XA[8] XA[7] XA[6] XA[5] XA[4] XA[3] XA[2] XA[1] XA[0] XD[15] XD[14] XD[13] XD[12] XD[11] XD[10] XD[9] XD[8] XD[7] XD[6] XD[5] XD[4] XD[3] XD[2] XD[1] XD[0] nCS[3] nCS[2] nCS[1] nCS[0] nWE nOE READY FCSN USB_DP USB_DN USBH_DP
Shared Signal
GPIO_B[0] GPO SD_nCLK / GPIO_B[1] DQM[0] DQM[1] DQS[1] DQS[0] SD_nRAS SD_nCAS SD_BA[1] SD_BA[0]
Ball
M10 N2 P2 L6 P3 M6 L7 P10 G5 N3 M5 M4 K4 L1 H1 K6 K7 H2 G1 H4 G2 J7 J9 H9 G9 H6 H5 J6 H7 H8 G8 H10 F9 E5 G6 G7 F7 E6 D9 E11 E10 M7 R2 M3 N1 J8 K10 J15 D12 P8 M9 R8
Type Description - TCC767
External Memory Interface Pins
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I/O SDRAM Clock Enable signal. Active high. / GPIO_B[0] SDRAM Clock / GPO. SD_CLK can be used as a general purpose output. Refer to section "MEMORY CONTROLLER". (MCFG register Bit[3] and Bit[1]) Chip select signal for SDRAM, Active low / Inverted SD_CLK for DDR SDRAM / GPIO_B[1] External Bus Address Bit [21] / Data I/O Mask 0 External Bus Address Bit [20] / Data I/O Mask 1 External Bus Address Bit [19] / DDR SDRAM Data Strobe [1] External Bus Address Bit [18] / DDR SDRAM Data Strobe [0] External Bus Address Bit [17] External Bus Address Bit [16] / SDRAM RAS signal External Bus Address Bit [15] / SDRAM CAS signal External Bus Address Bit [14] / SDRAM Bank Address 1 External Bus Address Bit [13] / SDRAM Bank Address 0. External Bus Address Bit [12] External Bus Address Bit [11] External Bus Address Bit [10] External Bus Address Bit [9] External Bus Address Bit [8] External Bus Address Bit [7] External Bus Address Bit [6] External Bus Address Bit [5] External Bus Address Bit [4] External Bus Address Bit [3] External Bus Address Bit [2] External Bus Address Bit [1] External Bus Address Bit [0] External Bus Data Bit [15] External Bus Data Bit [14] External Bus Data Bit [13] External Bus Data Bit [12] External Bus Data Bit [11] External Bus Data Bit [10] External Bus Data Bit [9] External Bus Data Bit [8] External Bus Data Bit [7] External Bus Data Bit [6] External Bus Data Bit [5] External Bus Data Bit [4] External Bus Data Bit [3] External Bus Data Bit [2] External Bus Data Bit [1] External Bus Data Bit [0] External Bus Chip Select 3 / GPIO_B[5] External Bus Chip Select 2 / GPIO_B[4] External Bus Chip Select 1 / GPIO_B[3] External Bus Chip Select 0 / GPIO_B[2] Static Memory Write Enable signal. Active low. Static Memory Output Enable signal. Active low. Ready information from external device. NOR Flash Chip Select. Should be connected to nCS[3].
GPIO_B[5] GPIO_B[4] GPIO_B[3] GPIO_B[2]
USB/UART/IrDA Interface Pins
GPIO_B[26] GPIO_B[27] GPIO_B[28] USB Function D+ signal / GPIO_B[26] USB Function D- signal / GPIO_B[27] USB Host D+ signal / GPIO_B[28]
Preliminary
1-27
TCC76x
Signal Name
USBH_DN UT_TX UT_RX BCLK LRCK MCLK DAO DAI CBCLK CLRCK CDAI EXINT[3] EXINT[2] EXINT[1] EXINT[0] GPIO_A[15] GPIO_A[14] GPIO_A[13] GPIO_A[12] GPIO_A[11] GPIO_A[10] GPIO_A[9] / BW[1]
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
GPIO_B[29] GPIO_B[8] / SD_nCS GPIO_B[9] GPIO_B[21] / BM[0] GPIO_B[22] / BM[1] GPIO_B[23] GPIO_B[24] / BM[2] GPIO_B[25] GPIO_A[1] GPIO_A[2] GPIO_A[3] GPIO_A[15] GPIO_A[14] / FGPIO[14] GPIO_A[13] / FGPIO[13] GPIO_A[12] / FGPIO[12] EXINT[3] EXINT[2] / FGPIO[14] EXINT[1] / FGPIO[13] EXINT[0] / FGPIO[12] SDI2 / FGPIO[11] / SCL FRM2 / FGPIO[10] / SDA SCK2 / FGPIO[9] / SCL
Ball
K9 L11 L10 M11 N12 M13 N14 N15 A7 A6 C7 E4 E3 D3 B3 E4 E3 D3 B3 E7 B1 D7
Type Description - TCC767
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O USB Host D- signal / GPIO_B[29] UART or IrDA TX data / GPIO_B[8] / DDR SDRAM Chip Select UART or IrDA RX data / GPIO_B[9]
Audio Interface Pins
I2S Bit Clock / GPIO_B[21] / Boot Mode Bit 0 I2S Word Clock / GPIO_B[22] / Boot Mode Bit 1 I2S System Clock / GPIO_B[23] I2S Digital Audio data Output / GPIO_B[24] / Boot Mode Bit 2 I2S Digital Audio data Input / GPIO_B[25]
CD DSP Interface Pins
CD Data Bit Clock Input / GPIO_A[1] CD Data Word Clock Input / GPIO_A[2] CD Data Input / GPIO_A[3]
External Interrupt Pins
External Interrupt Request [3] / GPIO_A[15] External Interrupt Request [2] / GPIO_A[14] / FGPIO[14] External Interrupt Request [1] / GPIO_A[13] / FGPIO[13] External Interrupt Request [0] / GPIO_A[12] / FGPIO[12]
General Purpose I/O Pins
GPIO_A[15] / External Interrupt Request 3 GPIO_A[14] / External Interrupt Request 2 / Fast GPIO bit 14 GPIO_A[13] / External Interrupt Request 1 / Fast GPIO bit 13 GPIO_A[12] / External Interrupt Request 0 / Fast GPIO bit 12 GPIO_A[11] / GSIO2 Data In / Fast GPIO bit 11 / I2C Clock. GPIO_A[10] / GSIO2 FRM / Fast GPIO bit 10 / I2C Data Line. GPIO_A[9] / Bus Width bit 1 / GSIO2 Clock / Fast GPIO bit 9 / I2C Clock. The status of BW[1:0] is latched at the rising edge of nRESET and used to determine external bus width. Refer to section "MEMORY CONTROLLER" for BW[1:0] description. GPIO_A[8] / Bus Width bit 0 / GSIO2 Data Out / Fast GPIO bits 8 / I2C Data Line. The status of BW[1:0] is latched at the rising edge of nRESET and used to determine external bus width. Refer to section "MEMORY CONTROLLER" for BW[1:0] description. GPIO_A[7] / GSIO1 Data In / Fast GPIO bit 7 GPIO_A[6] / GSIO1 FRM / Fast GPIO bit 6 GPIO_A[5] / GSIO1 Clock / Fast GPIO bit 5 GPIO_A[4] / GSIO1 Data Output / Fast GPIO bit 4 GPIO_A[3] / GSIO0 Data In / CD Interface Data / Fast GPIO bit 3 GPIO_A[2] / GSIO0 FRM / CD Interface LRCK / Fast GPIO bit 2 GPIO_A[1] / GSIO0 Clock / CD Interface BCLK / Fast GPIO bit 1 GPIO_A[0] / GSIO0 Data Out / FGPIO[0] GPIO_B[29] / USBH_DN GPIO_B[28] / USBH_DP GPIO_B[27] / USB_DN GPIO_B[26] / USB_DP GPIO_B[25] / I2S Interface Data In. GPIO_B[24] / Boot Mode bit 2 / I2S Interface Data Out. The status of BM[2:0] is latched at the rising edge of nRESET and used to determine the system boot mode. Refer to sections "BOOTING PROCEDURE" and "MEMORY CONTROLLER" for detailed description on BM[2:0]. GPIO_B[23] / I2S Interface Master Clock. GPIO_B[22] / Boot Mode bit 1 / I2S Interface LRCK. The status of BM[2:0] is latched at the rising edge of nRESET and used to determine the system boot mode. Refer to sections "BOOTING PROCEDURE" and "MEMORY CONTROLLER" for detailed description on BM[2:0].
GPIO_A[8] / BW[0] GPIO_A[7] GPIO_A[6] GPIO_A[5] GPIO_A[4] GPIO_A[3] GPIO_A[2] GPIO_A[1] GPIO_A[0] GPIO_B[29] GPIO_B[28] GPIO_B[27] GPIO_B[26] GPIO_B[25]
SDO2 / FGPIO[8] / SDA SDI1 / FGPIO[7] FRM1 / FGPIO[6] SCK1 / FGPIO[5] SDO1 / FGPIO[4] SDI0 / CDAI / FGPIO[3] FRM0 / CLRCK / FGPIO[2] SCK0 / CBCLK / FGPIO[1] SDO0 / FGPIO[0] USBH_DN USBH_DP USB_DN USB_DP DAI
A1 D5 C5 C8 B7 C7 A6 A7 B6 K9 R8 M9 P8 N15
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
GPIO_B[24] / BM[2]
DAO
N14
I/O
GPIO_B[23]
MCLK
M13
I/O
GPIO_B[22] / BM[1]
LRCK
N12
I/O
Preliminary
1-28
TCC76x
Signal Name Shared Signal
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Ball
Type Description - TCC767
GPIO_B[21] / Boot Mode bit 0 / I2S Interface BCLK. The status of BM[2:0] is latched at the rising edge of nRESET and used to determine the system boot mode. Refer to sections "BOOTING PROCEDURE" and "MEMORY CONTROLLER" for detailed description on BM[2:0]. GPIO_B[9 ] / UART RX Signal GPIO_B[8] / UART TX Signal / DDR SDRAM Chip Select GPIO_B[7] GPIO_B[5] / External Chip Select 3 GPIO_B[4] / External Chip Select 2 GPIO_B[3] / External Chip Select 1 GPIO_B[2] / External Chip Select 0 GPIO_B[1] / Chip select for SDRAM / Inverted Clock for DDR SDRAM. GPIO_B[0] / SDRAM clock control GPIO_D[17] / Fast GPIO bit 10 / I2C SCL GPIO_D[16] / Fast GPIO bit 9 / I2C SDA GPIO_D[15] / Fast GPIO bit 8
GPIO_B[21] / BM[0]
BCLK
M11
I/O
GPIO_B[9] GPIO_B[8] GPIO_B[7] GPIO_B[5] GPIO_B[4] GPIO_B[3] GPIO_B[2] GPIO_B[1] GPIO_B[0] GPIO_D[17] GPIO_D[16] GPIO_D[15] ADIN0 ADIN2 ADIN4
UT_RX UT_TX / SD_nCS nCS[3] nCS[2] nCS[1] nCS[0] SD_nCS / SD_nCLK SD_CKE FGPIO[10] / SCL FGPIO[9] / SDA FGPIO[8]
L10 L11 N11 M7 R2 M3 N1 P2 M10 E12 C14 B15 F14 G13 E15
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AI AI AI
ADC Input Pins
General purpose multi-channel ADC input 0 General purpose multi-channel ADC input 2 General purpose multi-channel ADC input 4
Clock Pins
XIN XOUT XFILT XTIN XTOUT XSCI XSCO TDI TMS TCK TDO nTRST K12 K11 G14 L13 M14 C2 B2 D11 C10 B11 A12 D10 I O AO I O I O I I I I/O I Main Crystal Oscillator Input for PLL. Input voltage must not exceed VDD_OSC (1.95V max). Main Crystal Oscillator Output for PLL PLL filter output Sub Crystal Oscillator Input. 32.768kHz is recommended. Input voltage must not exceed VDD_OSC (1.95V max). Sub Crystal Oscillator Output Crystal Oscillator Input for USB 2.0 Crystal Oscillator Output for USB 2.0
JTAG Interface Pins
JTAG serial data input for ARM940T JTAG test mode select for ARM940T JTAG test clock for ARM940T JTAG serial data output for ARM940T. External pull-up resistor is required to prevent floating during normal operation. JTAG reset signal for ARM940T. Active low.
Mode Control Pins
MODE1 PKG nRESET C13 F11 J11 I I I Mode Setting Input 1. Used for programming internal NOR flash. Pull-down for normal operation. Package ID. Pull-up for normal operation. System Reset. Active low.
USB 2.0 Interface Pins
DMRS DPRS DM DP RREF RPU E2 F4 C3 C1 B4 D1 I/O I/O I/O I/O I I USB 1.1 D- signal. Connect to external series resistor (391%). USB 1.1 D+ signal. Connect to external series resistor (391%). USB 2.0 D- signal. USB 2.0 D+ signal. Connect external reference resistor (12.1k1%) to ground (VSS_U20). Connect external pull-up resistor(1.5k1%) to USB 2.0 analog power (VDDA_U20).
MS & MSPRO Interface Pins
MS_CLK MS_BS MS_D[3] MS_D[2] L2 M2 M1 L3 O I/O I/O I/O MS/MSPRO Serial protocol Clock signal. MS/MSPRO Serial protocol Bus State signal. MS/MSPRO Data Line [3] MS/MSPRO Data Line [2]
Preliminary
1-29
TCC76x
Signal Name
MS_D[1] MS_D[0] MS_CD MS_PC MMC_CLK MMC_CMD MMC_D[3] MMC_D[2] MMC_D[1] MMC_D[0] MMC_CD MMC_PC
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
Ball
R1 P4 P7 K3 B13 A14 A11 B10 A13 B12 R5 J4
Type Description - TCC767
I/O I/O I O O I/O I/O I/O I/O I/O I O MS/MSPRO Data Line [1] MS/MSPRO Data Line [0] MS/MSPRO Card Detection Input. MS/MSPRO Power Control.
MMC & SD Interface Pins
MMC/SD Clock MMC/SD Command/Respond. MMC/SD Data Line [3]. MMC/SD Data Line [2]. MMC/SD Data Line [1]. MMC/SD Data Line [0]. MMC/SD Card Detection Input. MMC/SD Power Control. Memory Card Configuration Select Bit 2 MST Configuration Record in flash memory by AP Only support MMC/SD card Only support MS/MS_Pro/New MS card Support two kinds of card above. And MMC/SD is the first slot in USB mode. 100 Support two kinds of card above. And MS/MS_Pro/New MS card is the first slot in USB mode. Memory Card Configuration Select Bit 1 Memory Card Configuration Select Bit 0 111 001 010 011
MST[2]
R6
I
MST[1] MST[0] ND_D[15] ND_D[14] ND_D[13] ND_D[12] ND_D[11] ND_D[10] ND_D[9] ND_D[8] ND_D[7] ND_D[6] ND_D[5] ND_D[4] ND_D[3] ND_D[2] ND_D[1] ND_D[0] ND_nCE[1] ND_nCE[0] ND_ALE ND_CLE ND_nOE ND_nWE ND_nWP ND_RDY ND_WP_CTL PRTST AGN_nRESET
R7 N9 A15 B14 E13 D14 C15 F13 D15 E14 P15 N13 M12 R15 R14 P13 R13 P12 P6 R3 R10 N10 R9 P9 R12 R11 A10 K2 H15
I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O I I I O
Flash Memory Interface Pins
Flash Data Bus Bit 15 Flash Data Bus Bit 14 Flash Data Bus Bit 13 Flash Data Bus Bit 12 Flash Data Bus Bit 11 Flash Data Bus Bit 10 Flash Data Bus Bit 9 Flash Data Bus Bit 8 Flash Data Bus Bit 7 Flash Data Bus Bit 6 Flash Data Bus Bit 5 Flash Data Bus Bit 4 Flash Data Bus Bit 3 Flash Data Bus Bit 2 Flash Data Bus Bit 1 Flash Data Bus Bit 0 Flash Chip Enable 1, Low active. Flash Chip Enable 0, Low active. Flash Address Latch Enable, High active. Flash Command Latch Enable, High active. Flash Read Control signal, Low active. Flash Write Control signal, Low active. Flash Write Protect Control signal, Low active. Flash Ready/Busy signal. Pull-up resistor required. Flash Write Protect Control Enable. ND_nWP signal output is enabled when this signal is high. NAND Flash low level format control. Pull-up for normal operation (low level format disabled). Active low reset signal to AGAND Flash.
Miscellaneous Pins
ACT_nSPND ACS_IND J13 N4 O O Power Control Status Output. High indicates power on state (Access Mode), low indicates power off state (Suspend Mode). Flash Memory Access Indicator. This signal will be blinking when Flash Memory is accessed.
Preliminary
1-30
TCC76x
Signal Name
IIDE_INTRQ IIDE_nRESET IIDE_nCS3 IIDE_nCS1 IIDE_nUSB U_CF U_nRESET U_nEA U_nTEST TEST_MWP TEST_AG TEST_SP TESTEASL TESTHOE TESTHWE TESTREG TESTPACK TESTIS16 TESTIO7 TESTIO6 TESTIO5 TESTIO4 TESTCE4 TESTCE3 TESTCE2 TESTFAL TESTFCL TESTFRD TESTFWE VDDIO VDDIO VDDIO VDDIO VDDIO_USB VDD_NOR VDD_OSC VDDI VDDI VDDI VDDI VDDI VDDI VDDA_ADC VDDA_PLL VSSIO VSSIO VSSIO VSSIO VSSIO VSS_NOR VSSI VSSI VSSI VSSI VSSI VSSI
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
Ball
A3 B8 P5 P1 J14 G15 C11 H14 C12 N8 C4 A4 C9 N7 R4 J10 A8 A9 J3 J2 J1 K1 K13 M8 L8 L14 K15 M15 L15 F1 L5 J12 D8 P14 A2 K14 F5 H3 N5 G10 E8 D6 G11 H12 D4 L4 N6 L12 D13 E9 F3 K5 L9 F12 F8 F6
Type Description - TCC767
O I I I I I I I I I I I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND GND GND GND GND GND GND Active high Interrupt Request. This pin should be connected to one of EXINT[3:0]/GPIO_A[15:12] pins. Active low hardware reset. Chip Select 3 for the internal IDE interface. This signal should be connected to one of nCS[2:0]/GPIO_B[4:2]. Chip Select 1 for the internal IDE interface. This signal should be connected to one of nCS[2:0]/GPIO_B[4:2]. IDE / USB Mode Selection signal. 1: IDE Mode, 0: USB Mode. Internal IDE Mode Select Signal. For normal operation, connect this signal to IIDE_nUSB described above. Reset Signal EAMODE Select for Test. Pull-up for normal operation. Test Mode. (active low). Pull-up for normal operation. Reserved for Chip Test. Pull-up for normal operation. Reserved for Chip Test. Pull-down for normal operation. Reserved for Chip Test. Pull-down for normal operation. Reserved for Chip Test. Pull-down for normal operation. Reserved for Chip Test. Pull-down for normal operation. R eserved for Chip Test. Pull-up for normal operation. R eserved for Chip Test. Pull-up for normal operation. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test. Reserved for Chip Test.
Power Pins
Digital Power for I/O (3.3V) Digital Power for I/O (3.3V) Digital Power for I/O (3.3V) Digital Power for I/O (3.3V) Power for USB I/O (3.3V) Digital Power for NOR Flash (3.3V) Digital Power for Oscillators (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Analog Power for ADC (3.3V) Analog & Digital Power for PLL (1.8V) Digital Ground for I/O Digital Ground for I/O Digital Ground for I/O Digital Ground for I/O Digital Ground for I/O Digital Ground for NOR Flash Digital Ground for Internal Digital Ground for Internal Digital Ground for Internal Digital Ground for Internal Digital Ground for Internal Digital Ground for Internal
Preliminary
1-31
TCC76x
Signal Name
VSSA_ADC VSSA_PLL VDDA_U20 VDDA_U20 VDDA_U20 VDD_U20 VDD_U20 VDDI_U20 VDDI_U20 VO25 VSSA_U20 VSSA_U20 VSSA_U20 VSS_U20 VSS_U20 VSS_U20 VSS_U20
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
Ball
G12 H11 J5 E1 C6 K8 F10 B5 H13 G3 D2 F2 A5 F15 B9 G4 P11
Type Description - TCC767
GND GND PWR PWR PWR PWR PWR PWR PWR PWRO GND GND GND GND GND GND GND Analog Ground for ADC Analog Ground for PLL
Power Pins for USB 2.0
3.3V Analog Power for USB 2.0 3.3V for USB 2.0 3.3V for USB 2.0 3.3V for USB 2.0 3.3V for USB 2.0 2.5V Power for Internal. Connect to VO25. 2.5V Power for Internal. Connect to VO25. 2.5V Output. Connect to VDDI_U20. Ground for USB 2.0 Ground for USB 2.0 Ground for USB 2.0 Ground for USB 2.0 Ground for USB 2.0 Ground for USB 2.0 Ground for USB 2.0
Preliminary
1-32
TCC76x
1.4.6 TCC768 Pin Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Table 1.8 TCC768 Pin Description
Signal Name
SD_CKE SD_CLK SD_nCS XA[21] XA[20] XA[19] XA[18] XA[17] XA[16] XA[15] XA[14] XA[13] XA[12] XA[11] XA[10] XA[9] XA[8] XA[7] XA[6] XA[5] XA[4] XA[3] XA[2] XA[1] XA[0] XD[15] XD[14] XD[13] XD[12] XD[11] XD[10] XD[9] XD[8] XD[7] XD[6] XD[5] XD[4] XD[3] XD[2] XD[1] XD[0] NCS[3] NCS[2] NCS[1] NCS[0] ND_nWE nWE nOE READY
Shared Signal
GPIO_B[0] GPO GPIO_B[1] DQM[0] DQM[1]
Ball Type Description - TCC768
External Memory Interface Pins
J8 L5 L6 L4 K4 K3 L2 L3 G3 M3 M2 M1 J4 K2 M4 J1 H4 H5 H1 G6 H2 G5 G4 G7 G8 A3 F4 E2 E5 D8 F7 E1 F6 E3 D4 C2 B1 A7 B2 A10 F8 H6 J6 K6 J5 L10 M5 H7 J11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I SDRAM Clock Enable signal. Active high. / GPIO_B[0] SDRAM Clock / GPO. SD_CLK can be used as a general purpose output. Refer to section "MEMORY CONTROLLER". (MCFG register Bit[3] and Bit[1]) Chip select signal for SDRAM, Active low / GPIO_B[1] External Bus Address Bit [21] / Data I/O Mask 0 External Bus Address Bit [20] / Data I/O Mask 1 External Bus Address Bit [19] External Bus Address Bit [18] External Bus Address Bit [17] / CLE for NAND Flash External Bus Address Bit [16] / SDRAM RAS signal / ALE for NAND Flash External Bus Address Bit [15] / SDRAM CAS signal External Bus Address Bit [14] / SDRAM Bank Address 1 External Bus Address Bit [13] / SDRAM Bank Address 0. External Bus Address Bit [12] External Bus Address Bit [11] External Bus Address Bit [10] External Bus Address Bit [9] External Bus Address Bit [8] External Bus Address Bit [7] External Bus Address Bit [6] External Bus Address Bit [5] External Bus Address Bit [4] External Bus Address Bit [3] External Bus Address Bit [2] External Bus Address Bit [1] External Bus Address Bit [0] External Bus Data Bit [15] External Bus Data Bit [14] External Bus Data Bit [13] External Bus Data Bit [12] External Bus Data Bit [11] External Bus Data Bit [10] External Bus Data Bit [9] External Bus Data Bit [8] External Bus Data Bit [7] External Bus Data Bit [6] External Bus Data Bit [5] External Bus Data Bit [4] External Bus Data Bit [3] External Bus Data Bit [2] External Bus Data Bit [1] External Bus Data Bit [0] External Bus Chip Select [3] / NAND Flash Output Enable [3] / GPIO_B[5]. This pin should be connected to FCSN. External Bus Chip Select [2] / NAND Flash Output Enable [2] / GPIO_B[4] External Bus Chip Select [1] / NAND Flash Output Enable [1] / GPIO_B[3] External Bus Chip Select [0] / NAND Flash Output Enable [1] / GPIO_B[2] NAND flash WE. Active low. / GPIO_B[7] Static Memory Write Enable signal. Active low. Static Memory Output Enable signal. Active low. Ready information from external device.
ND_CLE SD_nRAS / ND_ALE SD_nCAS SD_BA[1] SD_BA[0]
ND_nOE[3] / GPIO_B[5] ND_nOE[2] / GPIO_B[4] ND_nOE[1] / GPIO_B[3] ND_nOE[0] / GPIO_B[2] GPIO_B[7]
Preliminary
1-33
TCC76x
Signal Name
FCSN USB_DP USB_DN USBH_DP USBH_DN UT_TX UT_RX GPIO_B[26] GPIO_B[27] GPIO_B[28] GPIO_B[29] GPIO_B[8] GPIO_B[9] / IDE_nCS1
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
Ball Type Description - TCC768
A12 L7 K8 L8 M9 M10 L9 I I/O I/O I/O I/O I/O I/O NOR Flash Chip Select. Should be connected to nCS[3].
USB/UART/IrDA Interface Pins
USB Function D+ signal / GPIO_B[26] USB Function D- signal / GPIO_B[27] USB Host D+ signal / GPIO_B[28] USB Host D- signal / GPIO_B[29] UART or IrDA TX data / GPIO_B[8] UART or IrDA RX data / GPIO_B[9] / IDE Chip Select 1
Audio Interface Pins
BCLK LRCK MCLK DAO DAI ADCDAT LCH_OUT RCH_OUT RCH_IN MIC_IN LCH_IN VMID MICBIAS WMODE SDIN SCLK CBCLK CLRCK CDAI EXINT[3] EXINT[2] EXINT[1] EXINT[0] GPIO_A[15] GPIO_A[14] GPIO_A[13] GPIO_A[12] GPIO_A[11] GPIO_A[10] GPIO_A[9] / BW[1] GPIO_A[8] / BW[0] GPIO_A[7] GPIO_A[6] GPIO_A[5] GPIO_A[4] GPIO_A[3] GPIO_A[2] GPIO_A[1] GPIO_A[0] GPIO_B[29] GPIO_B[28] GPIO_B[27] CSB GPIO_A[8] / BW[0] GPIO_A[9] / BW[1] GPIO_A[1] GPIO_A[2] GPIO_A[3] GPIO_A15 GPIO_A[14] / FGPIO[14] GPIO_A[13] / FGPIO[13] GPIO_A[12] / FGPIO[12] EXINT[3] EXINT[2] / FGPIO[14] EXINT[1] / FGPIO[13] EXINT[0] / FGPIO[12] SDI2 / FGPIO[11] / SCL FRM2 / FGPIO[10] / SDA SCK2 / FGPIO[9] / SCL SDO2 / FGPIO[8] / SDA SDI1 / FGPIO[7] FRM1 / FGPIO[6] SCK1 / FGPIO[5] SDO1 / FGPIO[4] SDI0 / CDAI / FGPIO[3] FRM0 / CLRCK / FGPIO[2] SCK0 / CBCLK / FGPIO[1] SDO0 / FGPIO[0] USBH_DN USBH_DP USB_DN GPIO_B[21] / BM[0] GPIO_B[22] / BM[1] GPIO_B[23] GPIO_B[24] / BM[2] GPIO_B[25] J9 L11 K12 K11 K10 H10 E11 E12 F1 A4 F2 B5 D5 F3 D6 E7 D9 E9 E8 A2 D3 B3 C3 A2 D3 B3 C3 E4 E6 E7 D6 B6 C6 B7 B8 E8 E9 D9 C9 M9 L8 K8 I/O I/O I/O I/O I/O O AO AO AI AI AI AO AO I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I2S Bit Clock / GPIO_B[21] / Boot Mode Bit 0. Internal pull-down resistor is active at power up. I2S Word Clock / GPIO_B[22] / Boot Mode Bit 1 Internal pull-down resistor is active at power up. I2S System Clock / GPIO_B[23] I2S Digital Audio data Output / GPIO_B[24] / Boot Mode Bit 2 I2S Digital Audio data Input / GPIO_B[25] I2S Digital Audio data Output of audio CODEC(ADC). Must be connected externally to GPIO_B25 (DAI) DAC Left Channel Output of audio CODEC DAC Right Channel Output of audio CODEC ADC Right Channel Input of audio CODEC Microphone Input of audio CODEC ADC Left Channel Input of internal audio CODEC Mid-rail reference decoupling point Microphone Bias CODEC I/F Control. Pull-down for normal operation. Internal pull-up resistor is active at power up. 2-Wire MCU Data Input for CODEC 2-Wire MCU Clock Input for CODEC
CD DSP Interface Pins
CD Data Bit Clock Input / GPIO_A[1] CD Data Word Clock Input / GPIO_A[2] CD Data Input / GPIO_A[3]
External Interrupt Pins
External Interrupt Request [3] / GPIO_A[15] External Interrupt Request [2] / GPIO_A[14] / FGPIO[14] External Interrupt Request [1] / GPIO_A[13] / FGPIO[13] External Interrupt Request [0] / GPIO_A[12] / FGPIO[12]
General Purpose I/O Pins
GPIO_A[15] / External Interrupt Request 3 GPIO_A[14] / External Interrupt 2 / Fast GPIO bit 14 GPIO_A[13] / External Interrupt 1 / Fast GPIO bit 13 GPIO_A[12] / External Interrupt 0 / Fast GPIO bit 12 GPIO_A[11] / GSIO2 Data In / Fast GPIO bit 11 / I2C Clock. GPIO_A[10] / GSIO2 FRM / Fast GPIO bit 10 / I2C Data Line. GPIO_A[9] / Bus Width bit 1. The status of BW[1:0] is latched at the rising edge of nRESET and used to determine external bus width. GPIO_A[8] / Bus Width bit 0. The status of BW[1:0] is latched at the rising edge of nRESET and used to determine external bus width. GPIO_A[7] / GSIO1 Data In / Fast GPIO bit 7 GPIO_A[6] / GSIO1 FRM / Fast GPIO bit 6 GPIO_A[5] / GSIO1 Clock / Fast GPIO bit 5 GPIO_A[4] / GSIO1 Data Out / Fast GPIO bit 4 GPIO_A[3] / GSIO0 Data In / CD Interface Data / Fast GPIO bit 3. GPIO_A[2] / GSIO0 FRM / CD Interface LRCK / Fast GPIO bit 2 GPIO_A[1] / GSIO0 Clock / CD Interface BCLK / Fast GPIO bit 1 GPIO_A[0] / GSIO0 Data Out / FGPIO[0] GPIO_B[29] / USBH_DN GPIO_B[28] / USBH_DP GPIO_B[27] / USB_DN
Preliminary
1-34
TCC76x
Signal Name
GPIO_B[26] GPIO_B[25] GPIO_B[24] / BM[2] GPIO_B[23] GPIO_B[22] / BM[1]
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
USB_DP DAI DAO MCLK LRCK
Ball Type Description - TCC768
L7 K10 K11 K12 L11 I/O I/O I/O I/O I/O GPIO_B[26] / USB_DP GPIO_B[25] / I2S Interface Data In. Should be connected externally to ADCDAT pin. GPIO_B[24] / Boot Mode bit 2 / I2S Interface Data Out. The status of BM[2:0] is latched at the rising edge of nRESET and used to determine the system boot mode. GPIO_B[23] / I2S Interface Master Clock. GPIO_B[22] / Boot Mode bit 1 / I2S Interface LRCK. The status of BM[2:0] is latched at the rising edge of nRESET and used to determine the system boot mode. Internal pull-down resistor is active at power up. GPIO_B[21] / Boot Mode bit 0 / I2S Interface BCLK. The status of BM[2:0] is latched at the rising edge of nRESET and used to determine the system boot mode. Internal pull-down resistor is active at power up. GPIO_B[9 ] / UART RX Signal GPIO_B[8] / UART TX Signal GPIO_B[7] / Write Enable for NAND Flash GPIO_B[5] / External Chip Select 3 GPIO_B[4] / External Chip Select 2 GPIO_B[3] / External Chip Select 1 GPIO_B[2] / External Chip Select 0 GPIO_B[1] / Chip select for SDRAM GPIO_B[0] / SDRAM clock control GPIO_D[17] / Fast GPIO bit 10 / I2C SCL GPIO_D[16] / Fast GPIO bit 9 / I2C SDA GPIO_D[15] / Fast GPIO bit 8
GPIO_B[21] / BM[0] GPIO_B[9] GPIO_B[8] GPIO_B[7] GPIO_B[5] GPIO_B[4] GPIO_B[3] GPIO_B[2] GPIO_B[1] GPIO_B[0] GPIO_D[17] GPIO_D[16] GPIO_D[15] ADIN_0 ADIN_2 ADIN_4
BCLK UT_RX UT_TX ND_nWE nCS[3] nCS[2] nCS[1] nCS[0] SD_nCS SD_CKE FGPIO[10] / SCL FGPIO[9] / SDA FGPIO[8]
J9 L9 M10 L10 H6 J6 K6 J5 L6 J8 G2 A9 G1 G10 F10 E10
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O AI AI AI
ADC Input Pins
General purpose multi-channel ADC input 0 General purpose multi-channel ADC input 2 General purpose multi-channel ADC input 4
Clock Pins
XIN XOUT XFILT XTIN XTOUT TDI TMS TCK TDO nTRST MODE1 PKG1 nRESET VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO_USB VDD_OSC H8 G9 G12 K9 J10 C11 D11 C10 D10 B10 B11 J7 J12 F5 L1 H9 D7 A8 D2 A6 M12 M11 I O AO I O I I I I/O I I I I PWR PWR PWR PWR PWR PWR PWR PWR PWR Main Crystal Oscillator Input for PLL. 12MHz Crystal must be used if USB Boot Mode is required. Input voltage must not exceed VDD_OSC (1.95V max). Main Crystal Oscillator Output for PLL PLL filter output. 350pF(10%) capacitor is required. Sub Crystal Oscillator Input. 32.768kHz is recommended. Input voltage must not exceed VDD_OSC (1.95V max). Sub Crystal Oscillator Output
JTAG Interface Pins
JTAG serial data input. External pull-up resistor is required. JTAG test mode select. External pull-up resistor is required. JTAG test clock. External pull-up resistor is required. JTAG serial data output. External pull-up resistor is required. JTAG reset signal. Active low.
Mode Control Pins
Mode Setting Input 1. Pull-down for normal operation. Package ID1. Pull-up for normal operation. System Reset. Active low.
Power Pins
Digital Power for I/O (3.3V) Digital Power for I/O (3.3V) Digital Power for I/O (3.3V) Digital Power for I/O (3.3V) Digital Power for I/O (3.3V) Digital Power for I/O (3.3V) Digital Power for I/O (3.3V) Power for USB I/O (3.3V) Digital Power for Oscillators (1.8V)
Preliminary
1-35
TCC76x
Signal Name
VDDI VDDI VDDI VDDI VDDI VDDI VDDA_ADC VDDA_PLL HPVDD VDDB_CDC VDDC_CDC AVDD VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSSIO VSS_CDC VSSI VSSI VSSI VSSI VSSI VSSI VSSA_ADC VSSA_PLL AGND
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Shared Signal
Ball Type Description - TCC768
C1 H3 J3 C8 C4 D12 F11 H11 F12 M8 M6 A5 A1 K1 K5 L12 B12 H12 B9 A11 M7 D1 J2 K7 C7 B4 F9 C12 G11 C5 PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Digital Power for Internal Core (1.8V) Analog Power for ADC (3.3V) Analog & Digital Power for PLL (1.8V) Analog Power for Headphone Amp Digital Buffer Power for CODEC Core Power for CODEC Analog Power for CODEC Digital Ground for I/O Digital Ground for I/O Digital Ground for I/O Digital Ground for I/O Digital Ground for I/O Digital Ground for I/O Digital Ground for I/O Digital Ground for I/O Digital Ground for CODEC Digital Ground for Internal Digital Ground for Internal Digital Ground for Internal Digital Ground for Internal Digital Ground for Internal Digital Ground for Internal Analog Ground for ADC Analog Ground for PLL Analog Ground for CODEC
Table 1.9 Pin Comparison - TCC763 vs. TCC768
Ball #
D2 H12 A8 B9 A6 A11 D12 F9
TCC763 Rev. 1
GPIO_D18 GPIO_D19 ROUT LOUT VDD_NOR VSS_NOR VDDI_ADC VSSI_ADC
TCC768
VDDIO VSSIO VDDIO VSSIO VDDIO VSSIO VDDI VSSI
Note
Power for I/O and Memory Ground for I/O and Memory Power for I/O and Memory Ground for I/O and Memory Power for I/O and Memory Ground for I/O and Memory Core power. (1.8V) Core ground.
Preliminary
1-36
TCC76x
1.5 Package
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
MCLK/GPIO_B23 66
DAO/GPIO_B24 67
DAI/GPIO_B25
VDDA_ADC
VBBA_ADC
VSSA_ADC
VDDA_PLL
VDDI_ADC
VBBA_PLL
VSSA_PLL
VSSI_ADC
GPIO_D21
GPIO_D20
GPIO_D19
GPIO_D18
GPIO_D17
GPIO_D16
GPIO_D15
VDD_OSC
nRESET
READY
XTOUT
VDDIO
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
VSSIO MODE1 TDI TMS TCK TDO nTRST SDO0/GPIO_A0 SCK0/GPIO_A1 SFRM0/GPIO_A2 SDI0/GPIO_A3 SDO1/GPIO_A4 VDDI VSSI SCK1/GPIO_A5 VDDIO SFRM1/GPIO_A6 SDI1/GPIO_A7 SDO2/GPIO_A8 SCK2/GPIO_A9 SFRM2/GPIO_A10 SDI2/GPIO_A11 VDDI VSSI EXINT0/GPIO_A12 EXINT1/GPIO_A13 EXINT2/GPIO_A14 EXINT3/GPIO_A15 XD0 XD1 XD2 XD3
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9
65
VSSIO
ADIN4
ADIN2
ADIN0
XOUT
XFILT
PKG1
XTIN
XIN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDD_USB LRCK/GPIO_B22 BCLK/GPIO_B21 UT_RX/IDE_nCS1/GPIO_B9 UT_TX/GPIO_B8 nOE nWE ND_nWE/GPIO_B7 SD_CKE/GPIO_B0 VSSI USBH_DN/GPIO_B29 USBH_DP/GPIO_B28 USB_DN/GPIO_B27 USB_DP/GPIO_B26 nCS3/nOE3/GPIO_B5 nCS2/nOE2/GPIO_B4 nCS1/nOE1/GPIO_B3 nCS0/nOE0/GPIO_B2 SD_nCS/GPIO_B1 VSSIO SD_CLK/GPO XA21/DQM0 XA20/DQM1 VDDI XA19 XA18 XA17/CLE XA16/nRAS/ALE XA15/nCAS XA14/BA1 XA13/BA0 VDDIO
TCC760
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
XD10
XD11
XD12
XD13
XD14
XD15
XA0
XA1
XA2
XA3
XA4
XA5
XA6
XA7
XA8
VSSIO
XA9
XA10
XA11
XA12
VDDIO
Figure 1.8 TCC760 Package Diagram (128-TQFP-1414 / Top View)
Preliminary
VSSIO
XD4
XD5
XD6
XD7
XD8
VSSI
XD9
VDDI
VDDI
VSSI
1-37
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 VSSIO VSSIO MODE1 TDI TMS TCK TDO nTRST HSYNC/GPIO_B17 VSYNC/GPIO_B18 PXCLK/GPIO_B19 ACBIAS/GPIO_B20 SDO0/GPIO_A0 SCK0/GPIO_A1 SFRM0/GPIO_A2 SDI0/GPIO_A3 GPIO_D7 PD4/GPIO_A28 PD5/GPIO_A29 PD6/GPIO_A30 PD7/GPIO_A31 SDO1/GPIO_A4 VDDI VSSI VSSI SCK1/GPIO_A5 VDDIO VDDIO SFRM1/GPIO_A6 SDI1/GPIO_A7 GPIO_D8 GPIO_D9 SDO2/GPIO_A8 SCK2/GPIO_A9 SFRM2/GPIO_A10 SDI2/GPIO_A11 GPIO_D10 GPIO_D11 GPIO_D12 GPIO_D13 VDDI VDDI VSSI GPIO_D14 EXINT0/GPIO_A12 EXINT1/GPIO_A13 EXINT2/GPIO_A14 EXINT3/GPIO_A15 XD0 XD1 XD2 XD3 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
GPIO_D21 GPIO_D20 GPIO_D19 GPIO_D18 GPIO_D17 GPIO_D16 GPIO_D15 PKG1 PKG0 VSSI_ADC VDDI_ADC VBBA_ADC VSSA_ADC ADIN7 ADIN6 ADIN5 ADIN4 ADIN3 ADIN2 ADIN1 ADIN0 VDDA_ADC VBBA_PLL VSSA_PLL XFILT VDDA_PLL PD3/GPIO_A27 PD2/GPIO_A26 PD1/GPIO_A25 PD0/GPIO_A24 PD15/GPIO_A23 PD14/GPIO_A22 VDDIO VDDIO PD13/GPIO_A21 PD12/GPIO_A20 XOUT XIN READY nRESET VDD_OSC PD11/GPIO_A19 PD10/GPIO_A18 PD9/GPIO_A17 PD8/GPIO_A16 XTOUT XTIN DAI/GPIO_B25 DAO/GPIO_B24 MCLK/GPIO_B23 VSSIO VSSIO
TCC761E
VDD_USB VDD_USB LRCK/GPIO_B22 BCLK/GPIO_B21 UT_RX/GPIO_B9 UT_TX/GPIO_B8 nOE nWE ND_nWE/GPIO_B7 SD_CKE/GPIO_B0 IDE_nCS1/GPIO_B6 GPIO_D6 VSSI USBH_DN/GPIO_B29 USBH_DP/GPIO_B28 USB_DN/GPIO_B27 USB_DP/GPIO_B26 CDAI/GPIO_B16 CLRCK/GPIO_B15 CBCLK/GPIO_B14 nCS3/nOE3/GPIO_B5 nCS2/nOE2/GPIO_B4 nCS1/nOE1/GPIO_B3 nCS0/nOE0/GPIO_B2 SD_nCS/GPIO_B1 VSSIO VSSIO SD_CLK/GPO XD31/GPIO_C15 XD30/GPIO_C14 XD29/GPIO_C13 XD28/GPIO_C12 XD27/GPIO_C11 XD26/GPIO_C10 XD25/GPIO_C9 XD24/GPIO_C8 XA23/DQM0 XA22/DQM1 XA21/DQM2 XA20/DQM3 GPIO_D5 VDDI GPIO_D4 XA19 XA18 XA17/CLE XA16/nRAS/ALE XA15/nCAS XA14/BA1 XA13/BA0 VDDIO VDDIO
Figure 1.9 TCC761-E Package Diagram (208-LQFP-2828 / Top View)
VSSIO VSSIO XD4 XD5 XD6 XD7 XD8 SDO3/GPIO_B10 SCK3/GPIO_B11 FRM3/GPIO_B12 SDI3/GPIO_B13 VDDI VSSI XD9 XD10 XD11 XD12 XD13 XD14 XD15 GPIO_D0 VDDIO VDDIO XD16/GPIO_C0 XD17/GPIO_C1 XD18/GPIO_C2 XD19/GPIO_C3 XD20/GPIO_C4 XD21/GPIO_C5 XD22/GPIO_C6 XD23/GPIO_C7 XA0 XA1 XA2 XA3 XA4 XA5 XA6 VDDI VSSI VSSI GPIO_D1 GPIO_D2 GPIO_D3 XA7 XA8 XA9 XA10 XA11 XA12 VSSIO VSSIO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Preliminary
1-38
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
VSSIO
B
XD5
C
XD6
D
GPIO_B11
E
VSSI
F
XD12
G
GPIO_D0
H
XD17
J
XD21
K
XA1
L
XA5
M
VSSI
N
GPIO_D3
P
XA7
R
XA10
T
XA11
U
VDDIO
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
XD0
XD3
VSSIO
XD7
GPIO_B12
XD9
XD13
VDDIO
XD18
XD22
XA2
XA6
GPIO_D1
XA8
XA12
VSSIO
XA14
GPIO_A15
XD1
XD2
XD8
GPIO_B13
XD10
XD14
VDDIO
XD19
XD23
XA3
VDDI
GPIO_D2
XA9
VSSIO
VDDIO
XA15
GPIO_A12 GPIO_A13 GPIO_A14
XD4
GPIO_B10
VDDI
XD11
XD15
XD16
XD20
XA0
XA4
VSSI
XA13
XA17
XA16
XA19
GPIO_D14
VDDI
VSSI
GPIO_D13
XA18
VDDI
GPIO_D4
XA20
VDDI
GPIO_D11 GPIO_D12 GPIO_A11
GPIO_D5
XA22
XA21
XD24
GPIO_D10
GPIO_A9 GPIO_A10 GPIO_D9
XA23
XD26
XD25
XD28
GPIO_A8
GPIO_A7
GPIO_D8
VDDIO
XD27
XD30
XD29
SD_CLK
GPIO_A6
GPIO_A5
VDDIO
VSSI
XD31
VSSIO
VSSIO
GPIO_B2
VSSI
GPIO_A4
VDDI
GPIO_A30
GPIO_B1
GPIO_B4
GPIO_B3 GPIO_B14
GPIO_A31 GPIO_A28 GPIO_A29 GPIO_A3
GPIO_B5 GPIO_B16 GPIO_B15
USB_DN
GPIO_D7
GPIO_A1
GPIO_A2 GPIO_B20
USB_DP
USBH_DN USBH_DP GPIO_D6
GPIO_A0
GPIO_B18 GPIO_B19
nTRST
VSSI
GPIO_B0
GPIO_B6
GPIO_B7
GPIO_B17
TCK
TDO
MODE1
VSSA_ADC
ADIN_4
ADIN_0
XFILT
GPIO_A25
VDDIO
XOUT
VDDI
GPIO_A16 GPIO_B23 GPIO_B8
nOE
nWE
TMS
VSSIO
GPIO_D20 GPIO_D16 VSSI_ADC
ADIN_7
ADIN_3
VDDA_ADC VDDA_PLL GPIO_A24
VDDIO
XIN
GPIO_A19
XTOUT
VDD_USB GPIO_B22 GPIO_B9
TDI
GPIO_D21 GPIO_D19 GPIO_D15 VDDI_ADC
ADIN_6
ADIN_2 VBBA_PLL GPIO_A27 GPIO_A23 GPIO_A21
MODE0
GPIO_A18
XTIN
VSSIO
VDD_USB GPIO_B21
VSSIO
GPIO_D18 GPIO_D17
PKG1
PKG0
VBBA_ADC
ADIN_5
ADIN_1
VSSA_PLL GPIO_A26 GPIO_A22 GPIO_A20
nRESET
GPIO_A17 GPIO_B25 GPIO_B24
VSSIO
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
Figure 1.10 TCC761-Y Package Diagram (208-TBGA-1515 / Bottom View)
Preliminary
1-39
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
A
B
C
D
E
F
G
H
J
K
L
M
VSSIO 1
XD4
VDDI
VSSI
XD9
RCH_IN
GPIO_D15
XA6
XA9
VSSIO
VDDIO
XA13 1
GPIO_A15 2
XD2
XD5
GPIO_D18
XD13
LCH_IN
GPIO_D17
XA4
VSSI
XA11
XA18
XA14 2
XD15 3
GPIO_A13
GPIO_A12 GPIO_A14
XD7
WMODE
XA16
VDDI
VDDI
XA19
XA17
XA15 3
MIC_IN 4
VSSI
VDDI
XD6
GPIO_A11
XD14
XA2
XA8
XA12
XA20
XA21
XA10 4
AVDD 5
VMID
AGND
MICBIAS
XD12
VDDIO
XA3
XA7
GPIO_B2
VSSIO
SD_CLK
nWE 5
VDD_NOR 6
GPIO_A7
GPIO_A6
GPIO_A8
GPIO_A10
XD8
XA5
GPIO_B5
GPIO_B4
GPIO_B3
GPIO_B1
VDDC_WF 6
XD3 7
GPIO_A5
VSSI
VDDIO
GPIO_A9
XD10
XA1
nOE
PKG
VSSI
USB_DP
VSS_WF 7
ROUT 8
GPIO_A4
VDDI
XD11
GPIO_A3
XD0
XA0
XIN
GPIO_B0
USB_DN
USBH_DP
VDDB_WF 8
GPIO_D16 9
LOUT
GPIO_A0
GPIO_A1
GPIO_A2
VSSI_ADC
XOUT
VDDIO
GPIO_B21
XTIN
GPIO_B9
USBH_DN 9
XD1 10
nTRST
TCK
TDO
ADIN_4
ADIN_2
ADIN_0
ADCDAT
XTOUT
GPIO_B25
GPIO_B7
GPIO_B8 10
VSS_NOR 11
MODE1
TDI
TMS
LCH_OUT VDDA_ADC VSSA_PLL VDDA_PLL
READY
GPIO_B24
GPIO_B22
VDD_OSC 11
FCSN 12
VSSIO
VSSA_ADC VDDI_ADC
RCH_OUT
HPVDD
XFILT
GPIO_D19
nRESET
GPIO_B23
VSSIO
VDDIO_USB 12
A
B
C
D
E
F
G
H
J
K
L
M
Figure 1.11 TCC763/TCC764 Package Diagram (144-BGA-1010 / Bottom View)
Preliminary
1-40
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
A 1 2 3
GPIO_A[14] EXINT[2] FGPIO[14] XD[8]
B
XD[7] GPIO_A[13] EXINT[1] FGPIO[13] DM
C
DPRS
D
XD[9]
E
XD[12]
F
RCH_IN
G
H
J
VO25
K
PRTST
L
MS_PC
M
XA[11]
N
ACS_IND
P
MS_D[3]
R
VSS_CDC
T
TESTCE3
VDDA_U20 WMODE
1 2 3
XD[5]
DMRS
VSSA_U20
XD[13]
VSSA_U20 VSS_U20
XA[3]
VDDI
XA[8]
VSSIO
XA[14] SD_BA[1] XA[13] SD_BA[0]
MS_CLK
ND_nCE[0]
MMC_CD
MIC_IN
VSS_NOR
XD[4]
RPU
XD[10]
VDDA_U20
VDDIO
XA[2]
XA[6]
XD[14]
XA[9] GPIO_A[0] SDO0 FGPIO[0] TESTIO4 XA[10]
MS_BS
ND_nCE[1]
TESTCE2
4
VMID
GPIO_A[9] BW[1] SCLK
DP
GPIO_A[15] EXINT[3]
VDDI
VSSI
LCH_IN
XA[0]
XA[5]
VSSI
XA[7]
XA[15] SD_nCAS
MMC_PC
VDDC_CDC
TESTHOE
4
5
AVDD
XSCO
RREF
XA[16] SD_nRAS
VSSIO
XD[6]
XD[3]
XD[15]
XA[1]
VSSIO
XA[18] DQS[0]
XA[12]
MS_D[2]
MS_D[1]
MS_CD
5
6
XSCI
VDDA_U20
MICBIAS GPIO_A[11] SDI2 FGPIO[11] SCL ROUT
VSSA_U20
GPIO_A[12] EXTINT[0] VDD_NOR FGPIO[12] TESTIRQ GPIO_A[8] BW[0] SDIN VDDI GPIO_A[10] FRM2 FGPIO[10] SDA GPIO_A[5] TESTUSB
XA[19] DQS[1]
VDDIO
GPIO_B[23] MCLK
GPIO_B[2] nCS[0] TESTCS0
MS_D[0]
VDDB_CDC
6
7
GPIO_A[6] TESTRST
GPIO_A[7] SDI1 FGPIO[7]
VSSI
XA[21] DQM[0]
VDDI
XA[20] DQM[1]
XA[17]
GPIO_B[4] nCS[2] TEST_MWP TESTCS2
7
8
VDDI_U20
AGND
VSSI GPIO_A[3] SDI0 CDAI FGPIO[3] TESTIO7
VDDIO
nRESET
GPIO_B[1] SD_nCS SD_nCLK
nWE
SD_CLK GPO
GPIO_B[3] USB_DN nCS[1] GPIO_B[27]
8
9
TEST_AG
TESTPACK
VDDI
XD[11]
GPIO_B[0] SD_CKE
GPIO_B[5] nCS[3]
VDD_U20
USB_DP TESTHWE GPIO_B[26]
MST[1]
9
10
TEST_SP
GPIO_A[4] SDO1 FGPIO[4]
LOUT
VSS_U20
GPIO_A[2] FRM0 CLRCK FGPIO[2] TESTIO6 GPIO_A[1] SCK0 CBCLK FGPIO[1] TESTIO5 VSSIO
XD[2]
GPIO_B[7]
VSSI
USBH_DN GPIO_B[29]
MST[2]
USBH_DP GPIO_B[28]
MST[0]
10
11
TESTEASL
TESTIS16
MMC_D[3]
nTRST
XD[0]
XTIN
GPIO_B[8] UT_TX SD_nCS
GPIO_B[9] UT_RX
ND_nOE
ND_ALE
ND_nWE
11
12 ND_WP_CTL 13 14 15 16
TDO
MMC_D[2]
TCK
nOE
TDI
VDDI
ADIN0
TESTREG VDDA_PLL XTOUT
VDDIO_USB
GPIO_B[21] BM[0] BCLK VSSIO
ND_nWP
ND_CLE
ND_RDY
12 13 14 15 16
TMS
U_nTEST
MODE1
PKG
VSSI
ADIN2
VDDA_ADC XFILT
READY
VDD_OSC GPIO_B[22] BM[1] LRCK U_nEA
GPIO_B[25] DAI GPIO_B[24] BM[2] DAO AGN_nRESET
ND_D[0]
ND_D[1]
VSS_U20
MMC_D[1]
MMC_D[0]
FCSN
GPIO_D[15] VDD_U20 FGPIO[8]
ND_D[9]
ADIN4
VSSA_PLL VSS_U20 ADCDAT
TESTFAL
XA[4]
ND_D[3]
ND_D[4]
MMC_CMD U_nRESET
GPIO_D[16] FGPIO[9] ND_D[14] SDA ND_D[13]
ND_D[11] ND_D[10] RCH_OUT LCH_OUT HPVDD
XOUT
TESTFCL
ND_D[6]
ND_D[5]
ND_D[2]
MMC_CLK
GPIO_D[17] FGPIO[10] ND_D[15] SCL
ND_D[12]
ND_D[8] VSSA_ADC
XD[1]
U_CF
VDDIO
XIN
ACT_nSPND
TESTCE4
TESTFWE
TESTFRD
ND_D[7]
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Figure 1.12 TCC766 Package Diagram (232-FPBGA-1414 / Bottom View)
Preliminary
1-41
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
A
GPIO_A[8]
B
GPIO_A[10] FRM2 SDA
C
DP
D
RPU
E
VDDA_U20
F
VDDIO
G
XA[6]
H
XA[10]
J
TESTIO5
K
TESTIO4
L
XA[11]
M
MS_D[3]
N
nCS[0] GPIO_B[2]
P
IIDE_nCS1
R
MS_D[1]
1
BW[0] SDO2
1
2
VDD_NOR
XSCO
XSCI
VSSA_U20
DMRS
VSSA_U20
XA[4]
XA[7]
TESTIO6
PRTST
MS_CLK
MS_BS
SD_CLK GPO XA[15]
SD_nCS SD_nCLK GPIO_B[1] XA[20] DQM[1] MS_D[0]
nCS[2] GPIO_B[4]
2
3 4 5 6
IIDE_INTRQ
GPIO_A[12] EXINT[0] RREF
DM
GPIO_A[13] GPIO_A[14] EXINT[1] VSSIO EXINT[2] GPIO_A[15]
VSSI
VO25
VDDI
TESTIO7
MS_PC
MS_D[2]
nCS[1]
GPIO_B[3] SD_nCAS XA[13] ACS_IND
ND_nCE[0]
3 4 5 6
TEST_SP
TEST_AG
EXINT[3] XD[7]
DPRS
VSS_U20
XA[5]
MMC_PC
XA[12]
VSSIO
SD_BA[0] XA[14] SD_BA[1] XA[19] DQS[1] nCS[3] GPIO_B[5]
TESTHWE
VSSA_U20 GPIO_A[2] CLRCK GPIO_A[1] CBCLK
VDDI_U20 GPIO_A[0] SDO0 GPIO_A[4] SDO1
GPIO_A[6] GPIO_A[7] FRM1 VDDA_U20 SDI1 VDDI
VDDI
XA[16]
XD[14]
VDDA_U20
VSSI
VDDIO XA[21] DQM[0] XA[18] DQS[0]
VDDI
IIDE_nCS3 MMC_CD
XD[3] GPIO_A[11] SDI2 SCL VDDI
VSSI
XD[6]
XD[15]
XD[13]
XA[9]
VSSIO
ND_nCE[1]
MST[2]
GPIO_A[3] GPIO_A[9] SDI0 CDAI GPIO_A[5] SCK1 TESTEASL BW[1] SCK2 VDDIO
7
XD[4]
XD[5]
XD[12]
XA[3]
XA[8]
TESTHOE
MS_CD
MST[1]
7
8 9 10
TESTPACK IIDE_nRESET
VSSI
XD[10]
XD[11]
nWE
VDD_U20 USBH_DN GPIO_B[29] nOE
TESTCE2
TESTCE3 TEST_MWP USB_DN GPIO_B[27] GPIO_B[0] GPIO_B[21] BM[0] BCLK GPIO_B[22] GPIO_B[7]
USB_DP
USBH_DP
GPIO_B[26] GPIO_B[28] ND_nWE ND_nOE
8 9 10
TESTIS16
VSS_U20
XD[2]
VSS_NOR
XD[8]
XA[0]
XA[1]
XA[2]
VSSI GPIO_B[9] UT_RX GPIO_B[8] UT_TX
MST[0]
ND_WP_CTL MMC_D[2]
TMS
nTRST
XD[0]
VDD_U20
VDDI
XD[9]
TESTREG
ND_CLE
XA[17]
ND_ALE
11
MMC_D[3]
TCK
U_nRESET
TDI
XD[1]
PKG
VDDA_ADC
VSSA_PLL
nRESET
XOUT
VSS_U20
ND_RDY
11
12
TDO
MMC_D[0]
U_nTEST
FCSN
GPIO_D[17] SCL
VSSI
VSSA_ADC
VDDA_PLL
VDDIO
XIN
VSSIO
ND_D[5]
BM[1] LRCK
ND_D[0]
ND_nWP
12
13
MMC_D[1]
MMC_CLK
MODE1
VSSIO
ND_D[13] ND_D[10]
ADIN2
VDDI_U20
ACT_nSPND
TESTCE4
XTIN
GPIO_B[23] MCLK
ND_D[6] GPIO_B[24]
ND_D[2]
ND_D[1]
13
14
MMC_CMD
ND_D[14]
GPIO_D[16] SDA
ND_D[12]
ND_D[8]
ADIN0
XFILT
U_nEA
IIDE_nUSB
VDD_OSC
TESTFAL
XTOUT
BM[2] DAO
VDDIO_USB
ND_D[3]
14
15
ND_D[15]
GPIO_D[15]
ND_D[11]
ND_D[9]
ADIN4
VSS_U20
U_CF
AGN_nRESET
READY
TESTFCL
TESTFWE
TESTFRD
GPIO_B[25] DAI
ND_D[7]
ND_D[4]
15
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
Figure 1.13 TCC767 Package Diagram (225-FPBGA-1313 / Bottom View)
Preliminary
1-42
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
A
B
C
D
E
F
G
H
J
K
L
M
VSSIO 1
XD4
VDDI
VSSI
XD9
RCH_IN
GPIO_D15
XA6
XA9
VSSIO
VDDIO
XA13 1
GPIO_A15 2
XD2
XD5
VDDIO
XD13
LCH_IN
GPIO_D17
XA4
VSSI
XA11
XA18
XA14 2
XD15 3
GPIO_A13
GPIO_A12 GPIO_A14
XD7
WMODE
XA16
VDDI
VDDI
XA19
XA17
XA15 3
MIC_IN 4
VSSI
VDDI
XD6
GPIO_A11
XD14
XA2
XA8
XA12
XA20
XA21
XA10 4
AVDD 5
VMID
AGND
MICBIAS
XD12
VDDIO
XA3
XA7
GPIO_B2
VSSIO
SD_CLK
nWE 5
VDDIO 6
GPIO_A7
GPIO_A6
GPIO_A8
GPIO_A10
XD8
XA5
GPIO_B5
GPIO_B4
GPIO_B3
GPIO_B1
VDDC_CDC 6
XD3 7
GPIO_A5
VSSI
VDDIO
GPIO_A9
XD10
XA1
nOE
PKG1
VSSI
USB_DP
VSS_CDC 7
VDDIO 8
GPIO_A4
VDDI
XD11
GPIO_A3
XD0
XA0
XIN
GPIO_B0
USB_DN
USBH_DP VDDB_CDC 8
GPIO_D16 9
VSSIO
GPIO_A0
GPIO_A1
GPIO_A2
VSSI
XOUT
VDDIO
GPIO_B21
XTIN
GPIO_B9
USBH_DN 9
XD1 10
nTRST
TCK
TDO
ADIN_4
ADIN_2
ADIN_0
ADCDAT
XTOUT
GPIO_B25
GPIO_B7
GPIO_B8 10
VSSIO 11
MODE1
TDI
TMS
LCH_OUT VDDA_ADC VSSA_PLL VDDA_PLL
READY
GPIO_B24
GPIO_B22
VDD_OSC 11
FCSN 12
VSSIO
VSSA_ADC
VDDI
RCH_OUT
HPVDD
XFILT
VSSIO
nRESET
GPIO_B23
VSSIO
VDDIO_USB 12
A
B
C
D
E
F
G
H
J
K
L
M
Figure 1.14 TCC768 Package Diagram (144-BGA-1010 / Bottom View)
Preliminary
1-43
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTRODUCTION
Preliminary
1-44
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ADDRESS & REGISTER MAP
2 ADDRESS & REGISTER MAP 2.1 Address Map
The TCC76x has fixed address maps for digital audio en-decoder system. The address space is separated MSB 4bits of address bus, the following table represents overall address space of TCC76x system. Table 2.1 Address Allocation Map of the TCC76x Address Space 0x00000000 ~ 0x0FFFFFFF 0x10000000 ~ 0x1FFFFFFF 0x20000000 ~ 0x2FFFFFFF 0x30000000 ~ 0x3FFFFFFF 0x40000000 ~ 0x4FFFFFFF 0x50000000 ~ 0x5FFFFFFF 0x60000000 ~ 0x6FFFFFFF 0x70000000 ~ 0x7FFFFFFF 0x80000000 ~ 0x8FFFFFFF 0x90000000 ~ 0x9FFFFFFF 0xA0000000 ~ 0xAFFFFFFF 0xB0000000 ~ 0xBFFFFFFF 0xC0000000 ~ 0xCFFFFFFF 0xD0000000 ~ 0xDFFFFFFF 0xE0000000 ~ 0xEFFFFFFF 0xF0000000 ~ 0xFFFFFFFF Device Name 1) if Remap is 0, External ROM of chip select 3 or internal ROM. 2) if Remap is 1, Other type memory according to base value. 3) if any other type of memory is not assigned to this area, then Internal SRAM is assigned. Not Used Assigned to SDRAM initially. Assigned to internal SRAM Assigned to chip select 0 Initially the configuration register is set to SRAM Assigned to chip select 1 Initially the configuration register is set to IDE type device Assigned to chip select 2 Initially the configuration register is set to NAND flash Assigned to chip select 3 Initially the configuration register is set to ROM Various internal peripheral devices
Not Used
Assigned to internal boot ROM Assigned to memory controller configuration register space
The address space (0x00000000 ~ 0x0FFFFFFF) is initially allocated to internal or external PROM for booting procedure, and a special flag exists in memory controller unit for remapping this space to other type of memories. That is, if the remap flag is set to 1, this space is released from the external ROM of chip select 3 or internal boot ROM. Refer to the description of memory controller for detailed operation. The TCC76x has one chip select for SDRAM, and four chip selects for other type of memories. Their address space is dependent on the configuration registers for each chip selects. The above address map is only at the initial state of the TCC76x; these maps can be changed at user requests. The TCC76x has various peripherals for controlling a digital audio en-decoder system. These peripherals can be configured appropriately by it's own registers that can be accessed through specially allocated address. These address maps are represented in the following table. In case of memory controller, its space is separated for preventing illegal accessing. Refer to corresponding sections for detail information of each peripheral.
Preliminary
2-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ADDRESS & REGISTER MAP
Table 2.2 Address Allocations for Internal Peripherals (Base = 0x80000000) Offset Address Space Peripheral 0x000 ~ 0x0FF DAI & CDIF 0x100 ~ 0x1FF Interrupt Controller 0x200 ~ 0x2FF Timer Counter 0x300 ~ 0x3FF GPIO 0x400 ~ 0x4FF Clock Generator & Power Management 0x500 ~ 0x5FF USB1.1 Device 0x600 ~ 0x6FF UART/IrDA 0x700 ~ 0x7FF GSIO (General Purpose Serial Input/Output) 0x800 ~ 0x8FF I2C 0x900 ~ 0x9FF ECC 0xA00 ~ 0xAFF ADC Control & Etc. 0xB00 ~ 0xBFF Camera Interface 0xC00 ~ 0xCFF Reserved 0xD00 ~ 0xDFF USB1.1 Host 0xE00 ~ 0xEFF DMA Controller 0xF00 ~ 0xFFF LCD controller (TCC761 only) Address decoding logic only monitors base address (for example, 0x8xxxxxxx, 0x4xxxxxxx, etc.), and bit11~bit8 of accessing address bus. There can be a lot of mirror images of address space that are repeated at every 4Kbyte boundary, user can access certain registers by these mirror images also, so care must be taken not to modify these registers unintentionally.
Preliminary
2-2
TCC76x
2.2 Register Map
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ADDRESS & REGISTER MAP
Name DADI_L0 DADI_R0 DADI_L1 DADI_R1 DADI_L2 DADI_R2 DADI_L3 DADI_R3 DADO_L0 DADO_R0 DADO_L1 DADO_R1 DADO_L2 DADO_R2 DADO_L3 DADO_R3 DAMR DAVC CDDI_0 CDDI_1 CDDI_2 CDDI_3 CICR
Table 2.3 DAI & CDIF Register Map (Base = 0x80000000) Address Type Reset Description 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x80 0x84 0x88 0x8C 0x90 R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W 0x0000 0x0000 0x0000 Digital Audio Left Input Register 0 Digital Audio Right Input Register 0 Digital Audio Left Input Register 1 Digital Audio Right Input Register 1 Digital Audio Right Input Register 2 Digital Audio Right Input Register 2 Digital Audio Right Input Register 3 Digital Audio Right Input Register 3 Digital Audio Left Output Register 0 Digital Audio Right Output Register 0 Digital Audio Left Output Register 1 Digital Audio Right Output Register 1 Digital Audio Left Output Register 2 Digital Audio Right Output Register 2 Digital Audio Left Output Register 3 Digital Audio Right Output Register 3 Digital Audio Mode Register Digital Audio Volume Control Register CD Digital Audio Input Register 0 CD Digital Audio Input Register 1 CD Digital Audio Input Register 2 CD Digital Audio Input Register 3 CD Interface Control Register
Name IEN CREQ IREQ IRQSEL ICFG MREQ TSTREQ IRQ FIQ MIRQ MFIQ TMODE SYNC WKUP
Table 2.4 Interrupt Controller Register Map (Base = 0x80000100) Address Type Reset Description 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 R/W W R R/W R/W R R/W R R R R R/W R/W R/W 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x000007C0 0x00000000 0x00000000 Interrupt Enable Register Clear Interrupt Request Register Interrupt Request Flag Register IRQ/FIQ Select Register External interrupt configuration register Masked interrupt request flag register Test Mode Register (must be remained zero) IRQ Raw Status (IREQ & IRQSEL) FIQ Raw Status (~IREQ & IRQSEL) Masked IRQ Status (IRQ & IEN) Masked FIQ Status (FIQ & IEN) Trigger Mode (0: edge, 1:level) Synchronizer Control Wakeup Control
Preliminary
2-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ADDRESS & REGISTER MAP
Name TCFG0 TCNT0 TREF0 TMREF0 TCFG1 TCNT1 TREF1 TMREF1 TCFG2 TCNT2 TREF2 TMREF2 TCFG3 TCNT3 TREF3 TMREF3 TCFG4 TCNT4 TREF4 TCFG5 TCNT5 TREF5 TIREQ TWDCFG TWDCLR TC32EN TC32LDV TC32CMP0 TC32CMP1 TC32PCNT TC32MCNT TC32EN
Table 2.5 Timer/Counter Register Map (Base = 0x80000200) Address Type Reset Description 0x0000 R/W 0x00 Timer/Counter 0 Configuration Register 0x0004 R/W 0x0000 Timer/Counter 0 Counter Register 0x0008 R/W 0xFFFF Timer/Counter 0 Reference Register 0x000C R/W 0x0000 Timer/Counter 0 Middle Reference Register 0x0010 R/W 0x00 Timer/Counter 1 Configuration Register 0x0014 R/W 0x0000 Timer/Counter 1 Counter Register 0x0018 R/W 0xFFFF Timer/Counter 1 Reference Register 0x001C R/W 0x0000 Timer/Counter 1 Middle Reference Register 0x0020 R/W 0x00 Timer/Counter 2 Configuration Register 0x0024 R/W 0x0000 Timer/Counter 2 Counter Register 0x0028 R/W 0xFFFF Timer/Counter 2 Reference Register 0x002C R/W 0x0000 Timer/Counter 2 Middle Reference Register 0x0030 R/W 0x00 Timer/Counter 3 Configuration Register 0x0034 R/W 0x0000 Timer/Counter 3 Counter Register 0x0038 R/W 0xFFFF Timer/Counter 3 Reference Register 0x003C R/W 0x0000 Timer/Counter 3 Middle Reference Register 0x0040 R/W 0x00 Timer/Counter 4 Configuration Register 0x0044 R/W 0x00000 Timer/Counter 4 Counter Register 0x0048 R/W 0xFFFFF Timer/Counter 4 Reference Register 0x0050 R/W 0x00 Timer/Counter 5 Configuration Register 0x0054 R/W 0x00000 Timer/Counter 5 Counter Register 0x0058 R/W 0xFFFFF Timer/Counter 5 Reference Register 0x0060 R/W 0x0000 Timer/Counter n Interrupt Request Register 0x0070 R/W 0x0000 Watchdog Timer Configuration Register 0x0074 W Watchdog Timer Clear Register 0x0080 R/W 0x00007FFF 32-bit Counter Enable / Pre-scale Value 0x0084 R/W 0x00000000 32-bit Counter Load Value 0x0088 R/W 0x00000000 32-bit Counter Match Value 0 0x008C R/W 0x00000000 32-bit Counter Match Value 1 0x0090 R/W 32-bit Counter Current Value (pre-scale counter) 0x0094 R/W 32-bit Counter Current Value (main counter) 0x0080 R/W 0x00007FFF 32-bit Counter Enable / Pre-scale Value
Preliminary
2-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ADDRESS & REGISTER MAP
Name GDATA_A GIOCON_A GSEL_A GTSEL_A GDATA_B GIOCON_B GSEL_B GTSEL_B GDATA_C GIOCON_C
Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24
Table 2.6 GPIO Register Map (Base = 0x80000300) Type Reset Description R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0xFFFFFFFF 0x00000000 0x00000000 0x00000000 0x3FFFFFFF 0x000000FF 0x3C0000FF 0x00000000 0xFFFF 0x0000 0x7FFF 0x0000 GPIO_A Data Register GPIO_A Direction Control Register GPIO_A Function Select Register 1 GPIO_A Function Select Register 2 GPIO_B Data Register GPIO_B Direction Control Register GPIO_B Function Select Register 1 GPIO_B Function Select Register 2 GPIO_C Data Register GPIO_C Direction Control Register GPIO_D Data Register GPIO_D Direction Control Register
GDATA_D 0x30 R/W GIOCON_D 0x34 R/W Shaded registers are only valid in TCC761.
Name CKCTRL PLLMODE SCLKmode DCLKmode EACLKmode EX1CLKmode UTCLKmode UBCLKmode LCLKmode TCLKmode GCLKmode CIFCLKmode SW_nRST PWDCTL DIVMODE HCLKSTOP
Table 2.7 Clock Generator Register Map (Base = 0x80000400) Address Type Reset Description 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x3C 0x40 0x44 0x48 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00007FFE 0x00002E02 0x00082000 0x00000800 0x00000000 0x00000000 0x000001BE 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x0000FEFF 0x00000000 0x00000000 0x00000000 Clock Control Register PLL Control Register System Clock Control Register DCLK (DAI/CODEC) Control Register ADCLK and EX2CLK Control Register EX1CLK Control Register UTCLK (UART) Control Register UBCLK (USB) Control Register LCLK (LCD) Control Register TCLK (Timer) Control Register GCLK (GSIO) Control Register CIFCLK Control Register Software Reset for each peripherals Power Down Control Divider Mode Enable (DCO Disable) HCLK Stop Control
Preliminary
2-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ADDRESS & REGISTER MAP
Name UBFADR UBPWR UBEIR UBIR UBEIEN UBIEN UBFRM1 UBFRM2 UBIDX MAXP INCSR1 INCSR2 OCSR1 OCSR2 OFIFO1 OFIFO2 EP0FIFO EP1FIFO EP2FIFO DMACON DMAEP1 DMAEP2
Address 0x00 0x04 0x08 0x18 0x1C 0x2C 0x30 0x34 0x38 0x40 0x44 0x48 0x50 0x54 0x58 0x5C 0x80 0x84 0x88 0xC0 0xC4 0xC8
Table 2.8 USB Register Map (Base = 0x80000500) Type Reset Description NON INDEXED REGISTERS R/W 0x00 Function Address Register R/W 0x00 Power Management Register R/W 0x00 Endpoint Interrupt Flag Register R/W 0x00 USB Interrupt Flag Register R/W 0x07 Endpoint Interrupt Enable Register R/W 0x04 Interrupt Enable Register R 0x00 Frame Number 1 Register R 0x00 Frame Number 2 Register W 0x00 Index Register COMMON INDEXED REGISTER R/W 0x01 IN Max Packet Register IN INDEXED REGISTERS R/W 0x00 IN CSR1 Register (EP0 CSR Register) R/W 0x20 IN CSR2 Register OUT INDEXED REGISTERS R 0x00 OUT CSR1 Register R/W 0x00 OUT CSR2 Register R 0x00 OUT FIFO Write Count 1 Register R 0x00 OUT FIFO Write Count 2 Register FIFO REGISTERS R/W Unknown EP0 FIFO Register R/W Unknown EP1 FIFO Register R/W Unknown EP2 FIFO Register DMA REGISTERS R/W 0x00 DMA Control Register R/W Unknown EP1 FIFO Access Register for DMA R/W Unknown EP2 FIFO Access Register for DMA
Preliminary
2-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ADDRESS & REGISTER MAP
Name HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcRmInterval HcFmRemaining HcFmNumber HcPeriodStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2
Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58
Table 2.9 USBH Register Map (Base = 0x80000D00) Type Reset Description R 0x00000010 R/W 0x00000000 R 0x00000000 Control and status registers R 0x00000000 R/W 0x00000000 W 0x00000000 R/W 0x00000000 R 0x00000000 R/W 0x00000000 Memory pointer registers R/W 0x00000000 R/W 0x00000000 R/W 0x00000000 R 0x00000000 R/W 0x00002EDF R/W 0x00000000 Frame counter registers R/W 0x00000000 R/W 0x00000000 R/W 0x00000628 R/W 0x02001202 R/W 0x00000000 Root hub registers R/W 0x00000000 R/W 0x00000100 R/W 0x00000100
Preliminary
2-7
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ADDRESS & REGISTER MAP
Name UTRXD UTTXD UTDL UTIR UTCR UTLSR IrDACFG1 IrDACFG2
Table 2.10 UART/IrDA Register Map (Base = 0x80000600) Address Type Reset Description 0x00 R Unknown Receiver Buffer Register 0x00 W Unknown Transmitter Holding Register 0x04 W 0x0000 Divisor Latch Register 0x08 R/W 0x000 Interrupt Register 0x0C R/W 0x000 UART Control Register 0x10 R 0x0101 Status Register 0x14 R/W 0x0003 IrDA Configuration Register 1 0x18 R/W 0x4da1 IrDA Configuration Register 2 Table 2.11 GSIO Register Map (Base = 0x80000700) Type Reset Description R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Unknown Unknown 0x0000 0x0000 Unknown Unknown 0x0000 Unknown Unknown 0x0000 Unknown Unknown 0x0000 Register Reset 0xFFFF 0x0000 0x0000 0x0000 0x0000 0x0000 GSIO0 Output Data Register GSIO0 Input Data Register GSIO0 Control Register GSIO Global Control Register GSIO1 Output Data Register GSIO1 Input Data Register GSIO1 Control Register GSIO2 Output Data Register GSIO2 Input Data Register GSIO2 Control Register GSIO3 Output Data Register GSIO3 Input Data Register GSIO3 Control Register Map (Base Address = 0x80000800) Description Clock Prescale register Control Register Transmit Register Command Register Receive Register Status Register
Name GSDO0 GSDI0 GSCR0 GSGCR GSDO1 GSDI1 GSCR1 GSDO2 GSDI2 GSCR2 GSDO3 GSDI3 GSCR3
Address 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x20 0x24 0x28 0x30 0x34 0x38
Name PRES CTRL TXR CMD RXR SR
Table 2.12 I2C Address Type 0x00 RW 0x04 RW 0x08 W 0x0C W 0x10 R 0x14 R
Preliminary
2-8
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ADDRESS & REGISTER MAP
Name ECC_CTRL ECC_BASE ECC_MASK ECC_CLR SLC_ECC0 SLC_ECC1 SLC_ECC2 SLC_ECC3 SLC_ECC4 SLC_ECC5 SLC_ECC6 SLC_ECC7 MLC_ECC0W MLC_ECC1W MLC_ECC0R MLC_ECC1R
Table 2.13 ECC Register Address Type Reset 0x00 R/W 0x00000000 0x04 R/W 0x00000000 0x08 R/W 0x00000000 0x0C W 0x10 R 0x00000000 0x14 R 0x00000000 0x18 R 0x00000000 0x1C R 0x00000000 0x20 R 0x00000000 0x24 R 0x00000000 0x28 R 0x00000000 0x2C R 0x00000000 0x40 W 0x44 W 0x48 R/W 0x00000000 0x4C R/W 0x00000000
Map (Base Address = 0x80000900) Description ECC Control Register Base Address for ECC Calculation Address mask for ECC area. Clear ECC output register 1st Block ECC output for SLC NAND 2nd Block ECC output for SLC NAND 3rd Block ECC output for SLC NAND 4th Block ECC output for SLC NAND 5th Block ECC output for SLC NAND 6th Block ECC output for SLC NAND 7th Block ECC output for SLC NAND 8th Block ECC output for SLC NAND MLC NAND ECC calculation register 0 MLC NAND ECC calculation register 1 Calculated ECC output 0 for MLC NAND Calculated ECC output 1 for MLC NAND
Name ADCCON ADCDATA USBCTR TSTSEL MISCCFG CFGPUA CFGPUB CFGPUC CFGPUD CFGDRVAL CFGDRVAH CFGDRVBL CFGDRVBH CFGDRVCL CFGDRVCH CFGDRVDL CFGDRVDH CFGDRVXL CFGDRVXH CFGSYS ADCCONA ADCSTATUS ADCCFG
Table 2.14 ADC Address 0x00 0x04 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x60 0x80 0x84 0x88
Interface & ETC Register Map (Base = 0x80000A00) Type Reset Description R/W 0x00000000 ADC Control Register R Unknown ADC Data Register R/W 0x00000004 USB Port Control Register R/W 0x00000000 Test Mode Control Register R/W 0x00000000 Miscellaneous Configuration Register R/W 0x00000000 Pull-up Enable for GPIO_A R/W 0x00000000 Pull-up Enable for GPIO_B R/W 0x00000000 Pull-up Enable for GPIO_C R/W 0x003C0000 Pull-up Enable for GPIO_D R/W 0x00000000 Buffer Drive Strength Select AL R/W 0x00000000 Buffer Drive Strength Select AH R/W 0x00000000 Buffer Drive Strength Select BL R/W 0x00000000 Buffer Drive Strength Select BH R/W 0x00000000 Buffer Drive Strength Select CL R/W 0x00000000 Buffer Drive Strength Select CH R/W 0x00000000 Buffer Drive Strength Select DL R/W 0x00000000 Buffer Drive Strength Select DH R/W 0x03FFFFFF Buffer Drive Strength Select XL R/W 0x04000000 Buffer Drive Strength Select XH R/W 0x00000000 System Configuration R/W 0x00000018 ADC Control Register A R/W Unknown ADC Status Register R/W 0x00002400 ADC Configuration Register
Preliminary
2-9
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ADDRESS & REGISTER MAP
Name CPCR 656FCR1 656FCR2 IICR1 IICR2 CDCR1 CDCR2 CDCR3 CDCR4 FIFOSTATE CIRQ ICCTRL
Table 2.15 CIF Register Map (Base Address = 0x80000B00) Address Type Reset Description 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C W W W W W W W W W R W/R W 0x00000402 0x06FF0000 0x0000010B 0x028001E0 0x00000000 0x00000003 0x20000000 0x28000000 0x2C000000 0x00000000 0x00000000 0x00000000 Color/Pattern Configuration Register CCIR656 Configuration Register 1 CCIR656 Configuration Register 2 Input Image Configuration Register 1 Input Image Configuration Register 2 CIF DMA Configuration Register Memory Address for Y Channel Memory Address for Cb(U) Channel Memory Address for Cr(V) Channel FIFO Status Register Interrupt & CIF Operating Register Image Clock Control
C H A N N E L 0 C H A N N E L 1
Name ST_SADR0 SPARAM0 C_SADR0 ST_DADR0 DPARAM0 C_DADR0 HCOUNT0 CHCTRL0 CHCONFIG ST_SADR1 SPARAM1 C_SADR1 ST_DADR1 DPARAM1 C_DADR1 HCOUNT1 CHCTRL1
Table 2.16 DMA Address 0x00 0x04/0x08 0x0C 0x10 0x14/0x18 0x1C 0x20 0x24 0x2C 0x30 0x34/0x38 0x3C 0x40 0x44/0x48 0x4C 0x50 0x54
Controller Register Type Reset R/W R/W R R/W R/W R R/W 0x00000000 R/W 0x00000000 R/W R/W R/W R R/W R/W R R/W 0x00000000 R/W 0x00000000
Map (Base = 0x80000E00) Description Start Address of Source Block Parameter of Source Block Current Address of Source Block Start Address of Destination Block Parameter of Destination Block Current Address of Destination Block Initial and Current Hop count Channel Control Register Channel Configuration Register Start Address of Source Block Parameter of Source Block Current Address of Source Block Start Address of Destination Block Parameter of Destination Block Current Address of Destination Block Initial and Current Hop count Channel Control Register
Preliminary
2-10
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ADDRESS & REGISTER MAP
Name LCTRL LCLKDIV LHTIME1 LHTIME2 LVTIME1 LVTIME2 LVTIME3 LVTIME4 LLUTRD LLUTGR LLUTBL LDP7L LDP7H LDP5 LDP4 LDP3 LDS LSTATUS LIM LIP LIS LIBA0 LICA0 LIBA1 LIBA2
Table 2.17 LCD Address Type 0x00 R/W 0x04 R/W 0x08 R/W 0x0C R/W 0x10 R/W 0x14 R/W 0x18 R/W 0x1C R/W 0x20 R/W 0x24 R/W 0x28 R/W 0x2C R/W 0x30 R/W 0x34 R/W 0x38 R/W 0x3C R/W 0x40 R/W 0x44 R/Clear 0x48 R/W 0x4C R/W 0x50 R/W 0x54 R/W 0x58 R 0x5C R/W 0x60 R/W
Controller Register Map (Base = 0x80000F00) Reset Description 0x00000006 control register 0x00000000 ac-bias clock and pixel clock divisor 0x00000000 Horizontal axis timing control register1 0x00000000 Horizontal axis timing control register2 0x00000000 Vertical axis timing control register1 0x00000000 Vertical axis timing control register2 0x00000000 Vertical axis timing control register3 0x00000000 Vertical axis timing control register4 0x00000000 Lookup table for red color 0x00000000 Lookup table for green color 0x00000000 Lookup table for blue color 0x4D2B3401 modulo 7 dithering pattern low register 0x0000003F modulo 7 dithering pattern high register 0x1D0B0610 modulo 5 dithering patterns 0x00000768 modulo 4 dithering patterns 0x00000034 Modulo 3 dithering patterns 0x00000000 Display size register 0x00000000 Status register 0x00000007 Interrupt mask register 0x00000000 Image position register 0x00000000 Image size register 0x00000000 Image base address register 0 0x00000000 Image current address register 0x00000000Image base address register 1 0x00000000 Image base address register 2
Preliminary
2-11
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ADDRESS & REGISTER MAP
Name SDCFG SDFSM MCFG TST
Table 2.18 Memory Controller Register Map (Base = 0xF0000000) Address Type Reset Description 0x00 0x04 0x08 0x0C R/W R R/W W 0x62E97010 0xZZZZ_02 0x00000000
SDRAM Configuration Register SDRAM FSM Status Register Miscellaneous Configuration Register Test mode register (must be remained zero) External Chip Select 0 Configuration Register CSCFG0 0x10 R/W 0x0B405649 (Initially set to SRAM) External Chip Select 1 Configuration Register 0x0150569A CSCFG1 0x14 R/W (Initially set to IDE) External Chip Select 2 Configuration Register (Initially CSCFG2 0x18 R/W 0x006056BA set to NAND) External Chip Select 3 Configuration Register 0x0A70569A CSCFG3 0x1C R/W (Initially set to NOR) CLKCFG 0x20 R/W 0xXXXXXX00 Memory Controller Clock Count Register SDCMD 0x24 W SDRAM Command Register Z means that it is determined by the status of some external pins. Table 2.19 NAND flash Register Map (Base = N * 0x10000000) Address Type Reset Description
Name
NDCMD 0x00 R/W Unknown Command Cycle Register NDLADR 0x04 W Linear Address Cycle Register NDBADR 0x08 W Block Address Cycle Register NDIADR 0x0C W Single Address Cycle Register NDDATA 0x10 R/W Unknown Data Access Cycle Register N represents BASE field of CSCFGn registers that is configured as NAND flash chip select.
Preliminary
2-12
TCC76x
3 CPU 3.1 Overview
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CPU
The TCC76x has adopted the ARM940T core for controlling system and processing various kinds of digital signals. It has a Harvard cache architecture with separate 4Kbyte data and 4Kbytes instruction caches, each with 4-word of line length. A protection unit allows eight regions of memory to be defined, each with individual cache and write buffer configurations and access permissions. The cache system is software configurable to provide highest average of performance or to meet the needs of real-time systems. The followings are key features of ARM940T core. CPU Cache Operating State Operating Mode Memory Format Address Space Instruction ARM940T 4KB for Data / 4KB for Instruction ARM state / THUMB state 7 different modes (SVC/UND/ABT/FIQ/IRQ/SYS/USR) Little endian (ARM940T itself supports big-endian type also, but the memory controller in the TCC76x only support for little-endian type) 32bit of 4Gbyte 32bit (in ARM state) / 16bit (in THUMB state)
Preliminary
3-1
TCC76x
3.2 Functional Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CPU
For detailed description of the CPU, refer to "ARM940T Technical Reference Manual". 3.2.1 Operating States The ARM9TDMI core allows user application programs to freely switch between ARM state using 32bit of instruction set and THUMB state using 16bit of instruction set. The switching between two states does not affect internal registers and operating modes. 3.2.2 Memory Formats The ARM940T itself can treat words in memory as being stored either in big-endian or little-endian, but in the TCC76x, there is only little-endian supported by the memory controller. The following figure illustrates the structure of little-endian type of memories.
Higher Address 31 0x99 0xFE 0x76 Lower Address Higher Address
24 23 16 15 87 0
0x66 0xDC 0x54
0xAA 0xBA 0x32
0x55 0x98 0x10
Word Value 0x9966AA55 4 0xFEDCBA98 0 0x76543210
8
Lower Address
Figure 3.1 Little-Endian Addresses of Bytes-Words 3.2.3 Instruction Length The instruction length can be either 32 bits (ARM state) or 16 bits (THUMB state). 3.2.4 Data Types ARM940T supports byte (8 bits), half-word (16 bits), and word (32 bits) data types. Words must be aligned to 4-byte boundaries and half words to 2-byte boundaries. 3.2.5 Operating Modes ARM940T supports seven modes of operation: USER (usr) FIQ (fiq) IRQ (irq) Supervisor (svc) Abort (abt) System (sys) Undefined (und) The normal ARM program execution mode Designed to support a data transfer or channel process Used for general purpose interrupt handling Protected mode for the operating system Entered after a data or instruction prefetch abort A privileged user mode for the operating system Entered when an undefined instruction is executed
Switching between these modes may be made under software control, or may be brought about by interrupts or exception processing. Most application programs will execute in User mode. The non-user mode known as privileged modes are entered in order to service interrupts or exceptions, or to access protected resources.
Preliminary
3-2
TCC76x
3.2.6 Coprocessor CP15
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CPU
The ARM940T cached processor macrocell includes the ARM9TDMI microprocessor core, instruction and data caches, a write-buffer, and a protection unit for defining the attributes of regions of memory. The ARM940T incorporates two coprocessors: CP14 which allows software access to the debug communications channel CP15 which allows configuration of the caches, protection unit, and other system options such as clock operation. The register map of CP15 is shown in the following table. Table 3.1 CP15 Register Map Register Function Access 0 ID code / Cache type note 1 Control Read / Write 2 Cacheable note 3 Write buffer control Read / Write 4 Reserved 5 Protection region access permissions note 6 Protection region base/size control note 7 Cache operations Write only 8 Reserved 9 Cache lockdown Read / Write 10 - 14 Reserved 15 Test Not accessed in normal operation NOTE: Register of 0, 2, 5, and 6 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. Refer to the register descriptions for further information.
3.2.7
Protection Unit The protection unit is used to partition memory and set individual protection attributes for each partition. The instruction address space and the data address space can each be divided up to 8 regions of variable size. The protection unit is programmed via CP15 registers 1, 2, 3, 5 and 6. Before the protection unit is enabled, at least one valid data and instruction region must be programmed. If they are not programmed, the ARM940T can enter a state that is recoverable only by reset. Setting bit 0 of the CP15 register 1 (the control register) enables the protection unit. When the protection unit is disabled, all instruction fetches are non-cacheable and all data accesses are non-cacheable and non-bufferable.
Preliminary
3-3
TCC76x
3.2.8 Caches and Write Buffer 3.2.8.1 Cache Architecture
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CPU
The ARM940T incorporates a 4KB of instruction cache, a 4KB of data cache, and an 8-word write buffer. The Icache and Dcache have similar architectures, as illustrated in the following figure.
WDATA[31:0] A[31:2] A[31:6]
SEG3 SEG2 SEG1 SEG0
Line Index 0 1 2
Address TAG
Word 0 Word 1 Word 2 Word 3
CAM
RAM
63
A[3:2]
A[5:4]
1 0
2
3
SEG3 SEG2 SEG1 SEG0
RDATA[31:0]
Figure 3.2 4KB Cache Architecture in ARM940T Each cache comprises four, fully associative 1KB segments which support singlecycle reads, and either one or two-cycle writes depending on the sequentiality of the access. Each cache segment consists of 64 CAM (Content Addressable Memory) rows which each select one of 64 RAM four-word long lines. during a cache access, a segment is selected and the access address is compared with the 64 TAGs in the CAM. If a match occurs (or a hit), the matched line is enabled and the data can be accessed. If none of the TAGs match (or a miss), then external memory must be accessed, unless the access is a buffered write in which case the write buffer is used. If a read access from a cacheable memory region misses, new data is loaded into one of the 64 row lines of the selected segment. This is an allocate on read-miss replacement policy. Selection is performed by a randomly clocked target row counter. Critical or frequently-accessed instructions or data can be locked into the cache by restricting the range of the target counter. Locked lines cannot be replaced and remain in the cache until they are unlocked or flushed. The CAM allows 64 address TAGs to be stored for an address that selects a given segment (64-way associativity). This reduces the chance of an address sequence in, Preliminary 3-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CPU
for example, a program loop that constantly selects the same segment, from replacing data that is required again in a later iteration of the loop. The overhead for high associativity is the need to store a larger TAG. In the case of the ARM940T, this is 26 bits per line. The address bits are assigned as follows: Bits 31:6 Selects an address tag in CAM Bits 5:4 Selects one of the four cache segments Bits 3:2 Selects a word in the cache line.
3.2.8.2 Instruction Cache The ARM940T has a 4KB Icache comprising four 64-way associative segments of 16 bytes per line per segment. The Icache uses the physical address generated by the processor core. It employs a policy of allocate on read-miss and is always reloaded one cache line (four words) at a time, through the external interface. The Icache is always disabled on reset.
3.2.8.3 Data Cache The ARM940T has a 4KB Dcache comprising 256 lines of 16 bytes (four words), arranged as four 64-way associative segments. It employs an allocate on read-miss policy, and is always reloaded a cache line (four words) at a time through the external interface. The Dcache supports both Write-back (WB) and Write-through (WT) modes. The GCd (Gated Cacheable for data) bit and the GBd (Gated Bufferable for data) bit control the Dcache behavior. For this reason, the protection unit must be enabled before the Dcache is enabled.
3.2.8.4 The Write Buffer The ARM940T provides a write buffer to improve system performance. The write buffer can buffer up to eight words of data and four separate non-sequential addresses. Write buffer behavior is controlled by the protection region attributes of the region that store being performed and by the Dcache and control bits (GCd and GBd) from the protection unit. These control bits are generated as follows: GCd bit GBd bit The GCd bit is generated from the cacheable attribute of the protection region AND the Dcache enable AND the protection unit enable. The GBd bit is generated from the bufferable attribute for the protection region AND the protection unit enable
All accesses are initially non-cacheable and non-bufferable until the protection unit has been programmed and enabled. It follows that the write buffer cannot be used while the protection unit is disabled. On reset, the buffer is flushed.
Preliminary
3-5
TCC76x
3.3 Clock Modes
3.3.1 About clocking modes
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CPU
The ARM940T has two clock inputs HCLK and FCLK that allow flexible clocking configurations. There are three different modes of operation, selected using bits 30 and 31 of CP15 register 1 (C1), the control register. These modes are: FastBus Synchronous Asynchronous The TCC76x does not support Synchronous Mode. Do not enable Synchronous Mode. The ARM940T is a pseudo-static desing and both clocks can be stopped. Typically when accessing slow memory systems or peripherals, wait states are applied using the HREADY signal. Refer to AMBA Specification for more details. 3.3.2 FastBus mode In this mode of operation the HCLK input is used to control: the internal ARM9TDMI cache operations the AMBA bus interface The FCLK input is ignored. This mode is typically used in systems with high-speed memories. 3.3.3 Asynchronous mode This mode is typically used in systems with low-speed memory. In this mode both the HCLK and FCLK inputs are used. HCLK is used to control the AMBA bus interface. FCLK is used to control the internal ARM9TDMI processor core and any cache operations. The one restriction is that FCLK must have a higher frequency than HCLK. An example is shown in Figure 3.3.
HCLK FCLK
Figure 3.3 Asynchronous Clocking Mode If the ARM940T performs an external access, the ARM940T switches to HCLK to perform the access. The delay when switching from FCLK to HCLK is a minimum of one HCLK cycle and a maximum of one and a half of HCLK cycles. An example of the clock switching is shown in Figure 3.4. When switching from HCLK to FCLK, the maximum delay is one FCLK cycle and the maximum delay is one and a half of FCLK cycles.
HCLK FCLK ECLK
Figure 3.4 Switching from FCLK to HCLK in asynchronous mode
Preliminary
3-6
TCC76x
4 DAI & CDIF
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DAI & CDIF
4.1 DAI (Digital Audio Interface)
The block diagram of DAI is shown in Figure 4.1. The TCC76x provides digital audio interface that complies with IIS (Inter-IC Sound). The DAI has five input/output pins for IIS interface, MCLK, BCLK, LRCK, DAI and DAO. All DAI input/output pins are multiplexed with GPIO pins; GPIO_B<21:25>. The MCLK is the system clock pin that is used for CODEC system clock. In master mode, the MCLK can be generated from clock generator in which that is known as a DCLK, or fed from the outside of chip in slave mode. The DAI can process 256fs, 384fs and 512fs as a system clock. 256fs means that the system clock has 256 times of sampling frequency (fs). The BCLK is the serial bit clock for IIS data exchange. The DAI can generate 64fs, 48fs and 32fs by dividing a system clock. The polarity of BCLK can be programmed. That is, the serial bit can be stable either rising edge of BCLK or falling edge of BCLK. The LRCK is the frame clock for the stereo audio channel Left and Right. The frequency of LRCK is known as the "fs" - sampling frequency. Generally, for audio application such as MP3 Player and CD player, the fs can be set to 8kHz, 16kHz, 11.05kHz, 24kHz, 32kHz, 44.1kHz and 48kHz. For supporting the wide range of sampling frequency in audio application, the DCO function is very useful to generate a system clock. Refer the chapter of clock generator for detail information. All three clocks (MCLK, BCLK, LRCK) are selectable as master or slave. The DAI, DAO are the serial data input output pins respectively. The DAI has two 8-word input/output buffers. It has a banked buffer structure so that one side of buffer is receiving/transmitting data while the other side of that can be read/written through the DADI_XX/DADO_XX registers. The maximum data word size is 24 bit. Data is justified to MSB of 32bits and zeros are padded to LSB. There are two types of interrupt from IIS; transmit done interrupt, receive done interrupt. The transmit-done interrupt is generated when the 8 words are transferred successfully in the output buffer. At this interrupt, user should fill another 8 more words into the other part of the output buffer in the interrupt service routine (ISR). In this ISR routine, 8 consecutive stores of word data to the DADO registers are needed. The receive-done interrupt is generated when the 8 words are received successfully in the input buffer. At this interrupt, user should read 8 received words from the input buffer using 8 consecutive load instructions from the DADI registers.
Preliminary
4-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DAI & CDIF
Input Buffer DADI_L0 DADI_R0 DADI_L3 DADI_R3 LEFT0 RIGHT0 LEFT3 RIGHT3 LEFT4 Input Buffer Pointer RIGHT4 LEFT7 RIGHT7 MM CDIF Data CC Output Buffer IIS_SDO DADO_L0 DADO_R0 DADO_L3 DADO_R3 LEFT0 RIGHT0 LEFT3 RIGHT3 LEFT4 RIGHT4 Output Buffer Pointer LEFT7 RIGHT7 P2S LB DAVC S2P IIS_SDI
DCO SM
IIS_MCLK
DIVIDER CDIF BCLK CC BM IIS_BCLK
CDIF LRCK DIVIDER CC FM IIS_LRCK
Figure 4.1 DAI Block Diagram
Preliminary
4-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DAI & CDIF
LRCK
16 15 14 13 12
Left 11 10 9 8 7 6 5 4 3 2 1
Right 16
BCLK DAI/O
L S B M S B L S B M S B
MD=0 (IIS mode), BP=0, BCLK = 32fs
LRCK
32 31 30 29 28 27
Left 10 9 8 7 6 5 4 3 2 1 32
Right
BCLK DAI/O
M S B L S B M S B
MD=1(MSB justified mode), BP=0, BCLK=64fs
LRCK
24 23 22 21 20 21
Left 9 8 7 6 5 4 3 2 1
Right
BCLK DAI/O
M S B L S B M S B
MD=1(MSB justified mode), BP=1, BCLK=48fs
Figure 4.2 DAI Bus Timing Diagram
Preliminary
4-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DAI & CDIF
4.2 Register Description - DAI
Table 4.1 DAI Register Map (Base Address = 0x80000000) Name Address Type Reset Description DADI_L0 0x00 R Digital Audio Left Input Register 0 DADI_R0 0x04 R Digital Audio Right Input Register 0 DADI_L1 0x08 R Digital Audio Left Input Register 1 DADI_R1 0x0C R Digital Audio Right Input Register 1 DADI_L2 0x10 R Digital Audio Right Input Register 2 DADI_R2 0x14 R Digital Audio Right Input Register 2 DADI_L3 0x18 R Digital Audio Right Input Register 3 DADI_R3 0x1C R Digital Audio Right Input Register 3 DADO_L0 0x20 R/W Digital Audio Left Output Register 0 DADO_R0 0x24 R/W Digital Audio Right Output Register 0 DADO_L1 0x28 R/W Digital Audio Left Output Register 1 DADO_R1 0x2C R/W Digital Audio Right Output Register 1 DADO_L2 0x30 R/W Digital Audio Left Output Register 2 DADO_R2 0x34 R/W Digital Audio Right Output Register 2 DADO_L3 0x38 R/W Digital Audio Left Output Register 3 DADO_R3 0x3C R/W Digital Audio Right Output Register 3 DAMR 0x40 R/W 0x0000 Digital Audio Mode Register DAVC 0x44 R/W 0x0000 Digital Audio Volume Control Register
Digital Audio Mode Register (DAMR) 31 30 29 28 27 26 25 24 23 22 Reserved 15 14 13 12 11 10 9 8 7 6 EN TE RE MD SM BM FM CC BD<1:0> EN [15] 0 1 TE [14] 0 1 RE [13] 0 1 MD [12] 0 1
21
20
19 3 BP
0x80000040 18 17 16 2 CM 1 MM 0 LB
5 4 FD<1:0>
DAI Master Enable Disable DAI module Enable DAI module DAI Transmitter Enable Disable DAI transmitter Enable DAI transmitter DAI Receiver Enable Disable DAI receiver Enable DAI receiver DAI Bus Mode Set DAI bus as IIS bus mode Set DAI bus as MSB justified mode
SM [11] DAI System Clock Master Select 0 Set that DAI system clock is come from external pin 1 Set that DAI system clock is generated by the clock generator block The DAI system clock in clock generator is known as DCLK. It's frequency can be determined by setting DCLKmode register.
Preliminary
4-4
TCC76x
BM [10] 0 1 FM [9] 0 1 CC [8] 0 1 BD [7:6] 00 01 10 11
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DAI & CDIF
DAI Bit Clock Master Select Set that DAI bit clock is come from external pin Set that DAI bit clock is generated by dividing DAI system clock DAI Frame Clock Master Select Set that DAI frame clock is come from external pin Set that DAI frame clock is generated by dividing DAI bit clock CDIF Clock Select Disable CDIF Clock master mode Enable CDIF Clock master mode DAI Bit Clock Divider select Select Div 4 ( 256fs->64fs ) Select Div 6 ( 384fs->64fs ) Select Div 8 ( 512fs->64fs, 384fs->48fs , 256fs->32fs) Select Div16 ( 512fs->32fs )
FD [5:4] DAI Frame Clock Divider select 00 Select Div 32 ( 32fs->fs ) 01 Select Div 48 ( 48fs->fs ) 10 Select Div 64 ( 64fs->fs ) The combination of BD & FD determines that the ratio between main system clock and the sampling frequency. The multiplication between the division factor of BD and FD must be equal to this ratio. BP [3] 0 1 CM [2] 0 1 MM [1] 0 1 LB [0] 0 1 DAI Bit Clock Polarity Set that data is captured at positive edge of bit clock Set that data is captured at negative edge of bit clock CDIF Monitor Mode Disable CDIF monitor mode Enable CDIF monitor mode. Data bypass from CDIF DAI Monitor Mode Disable DAI monitor mode Enable DAI monitor mode. Transmitter should be enabled. (TE = 1) DAI Loop-back Mode Disable DAI Loop back mode Enable DAI Loop back mode 0x80000044 18 17 16 2 1 VC<3:0> 0
Digital Audio Volume Control Register (DAVC) 31 30 29 28 27 26 25 24 23 22 Reserved 15 14 13 12 11 10 9 8 7 6 Reserved
21 5
20 4
19 3
The volume of audio output can be manipulated by this register. It has -6dB unit so the output
Preliminary
4-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DAI & CDIF
volume can be set from 0 dB to -90 dB as the following table. VC [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 DAI Volume control 0dB -6dB -12dB -18dB -24dB -30dB -36dB -42dB -48dB -54dB -60dB -66dB -72dB -78dB -84dB -90dB
Preliminary
4-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DAI & CDIF
4.3 CDIF (CD-DSP Interface)
The block diagram of CDIF is illustrated in Figure 4.3. The TCC76x provides CD-ROM interface for feasible implementation of CD-ROM application such as CD-MP3 player. The CDIF supports the industry standard IIS format and the LSB justified format that is used as the most popular format for CD-ROM interface by Sony and Samsung. The CDIF has three pins for interface; CBCLK, CLRCK, CDAI. These are multiplexed with GPIO_B14, GPIO_B15 and GPIO_B16, respectively in the TCC76x or with GPIO_A1, GPIO_A2 and GPIO_A3 in other derivatives of the TCC76x. The CBCLK is the bit clock input pins of which frequency can be programmed by CICR for selection of 48fs and 32fs. The CLRCK is the frame clock input pin that indicates the channel of CD stereo digital audio data. The CDAI is the input data pin. The CDIF has five registers; CDDI_0 to CDDI_3 and CICR. The CDDI_0 to the CDDI_3 are the banked read only registers for access of data input buffer. The data input buffer is composed of sixteen 32 bit wide registers of which upper 16 bit is left channel data and lower is right channel data. The CDIF receive the serial data from CDAI pin and store the data into the buffer through the serial to parallel register. Whenever the half of buffer is filled, the receive interrupt is generated. Only the half of input buffer can be accessible through the CDDI_0 to the CDDI_3.
Input Buffer CDDI0 LEFT0 RIGHT0 CDDI3 LEFT3 RIGHT3 S2P LEFT4 RIGHT4 Input Buffer Pointer LEFT7 RIGHT7 CBCLK CDAI
CLRCK
Figure 4.3 CDIF Block Diagram
Preliminary
4-7
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DAI & CDIF
CLRCK
24 23 22 21 20
Left 19 10 9 8 7 6 5 4 3 2 1
Right 16
CBCLK CDAI
M S B L S B M S B
MD=0 (IIS mode), BP=0, CBCLK=48fs
CLRCK
24 23 22 21 20 19
Left 18 17 16 15 6 5 4 3 2 1
Right
CBCLK CDAI
M S B L S B
MD=1(LSB justified mode), BP=0, CBCLK=48fs Figure 4.4 CDIF Bus Timing Diagram
Preliminary
4-8
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DAI & CDIF
4.4 Register Description - CDIF
Table 4.2 CDIF Register Map (Base Address = 0x80000080) Name Address Type Reset Description CDDI_0 CDDI_1 CDDI_2 CDDI_3 CICR 0x80 0x84 0x88 0x8C 0x90 R R R R R/W CD Digital Audio Input Register 0 CD Digital Audio Input Register 1 CD Digital Audio Input Register 2 CD Digital Audio Input Register 3 CD Interface Control Register
0x0000
CD Data Input (CDDI0) 31 30 29 28 27 15 14 13 12 11
26 10
25
24 23 22 Left Channel Data 9 8 7 6 Right Channel Data
21 5
20 4
19 3
0x80000080 18 17 16 2 1 0
CD Data Input (CDDI1) 31 30 29 28 27 15 14 13 12 11
26 10
25
24 23 22 Left Channel Data 9 8 7 6 Right Channel Data
21 5
20 4
19 3
0x80000084 18 17 16 2 1 0
CD Data Input (CDDI2) 31 30 29 28 27 15 14 13 12 11
26 10
25
24 23 22 Left Channel Data 9 8 7 6 Right Channel Data
21 5
20 4
19 3
0x80000088 18 17 16 2 1 0
CD Data Input (CDDI3) 31 30 29 28 27 15 14 13 12 11
26 10
25
24 23 22 Left Channel Data 9 8 7 6 Right Channel Data
21 5
20 4
19 3
0x8000008C 18 17 16 2 1 0
CD Interface Control Register (CICR) 31 30 29 28 27 26 25 24 23 Reserved 15 14 13 12 11 10 9 8 7 Reserved EN [7] 0 1 EN
22 6
21 5 Reserved
20 4
19 3 BS
0x80000090 18 17 16 2 1 MD 0 BP
CDIF Enable Disable CDIF Enable CDIF
Preliminary
4-9
TCC76x
BS [3:2] 00 01 10 MD [1] 0 1 BP [0] 0 1
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DAI & CDIF
CDIF Bit Clock select 64fs 32fs 48fs Interface Mode select Select IIS format Select LSB justified format CDIF Bit Clock Polarity Set that data is captured at positive edge of bit clock Set that data is captured at negative edge of bit clock
Preliminary
4-10
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTERRUPT CONTROLLER
5 INTERRUPT CONTROLLER 5.1 Overview
The following figure represents the block diagram of interrupt controller. Interrupt controller can manage up to 19 interrupt sources. In the TCC76x, there are four external interrupt sources. The polarity and edge of the external interrupts are all programmable. There are four dedicated noise filter for each external interrupt source. There are two types of interrupt in ARM940T; IRQ type, FIQ type. Interrupt controller can select these two types for each interrupt source individually. The WakeUp Event control logic is provided to generate fully asynchronous wakeup signal for Power Down Mode or IDLE Mode.
Internal Interrupt Sources INTIN[18:4]
WakeUp Event (Asynchronous) Sync Noise Filter Edge/Level Selector
to Clock Generator Wakeup Control
External Interrupt Sources EXTIN[3:0]
ICFG IREQ IRQ Flag APB CREQ MREQ IEN IRQSEL nIRQ/nFIQ Generator nIRQ to ARM940T nFIQ
Figure 5.1 Interrupt Controller Block Diagram
Preliminary
5-1
TCC76x
5.2 Register Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTERRUPT CONTROLLER
Table 5.1 Interrupt Controller Register Map (Base Address = 0x80000100) Name Address Type Reset Description IEN CREQ IREQ IRQSEL ICFG MREQ TSTREQ IRQ FIQ MIRQ MFIQ TMODE SYNC WKUP Caution) 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 R/W W R R/W R/W R R/W R R R R R/W R/W R/W 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x000007C0 0x00000000 0x00000000 Interrupt Enable Register Clear Interrupt Request Register Interrupt Request Flag Register IRQ/FIQ Select Register External Interrupt Configuration Register Masked Interrupt Request Flag Register Test Mode Register (must be remained zero) IRQ Raw Status (IREQ & IRQSEL) FIQ Raw Status (~IREQ & IRQSEL) Masked IRQ Status (IRQ & IEN) Masked FIQ Status (FIQ & IEN) Trigger Mode (0: edge, 1:level) Synchronizer Control Wakeup Control
Some peripherals have their own request flags as well as the flag in interrupt controller, so in the interrupt service routine, user should clear their own request flags in the peripherals ahead of clearing the flag in the interrupt controller. The following pseudo code illustrates the sequence of processing the timer interrupt flags. if (MREQ & TimerREQ) { if (TIREQ & Timer0) { process_timer0(); TIREQ = Timer0; } if (TIREQ & Timer1) { process_timer1(); TIREQ = Timer1; } if (TIREQ & Timer2) { process_timer2(); TIREQ = Timer2; } if (TIREQ & Timer3) { process_timer3(); TIREQ = Timer3; } if (TIREQ & Timer4) { process_timer4(); TIREQ = Timer4; } if (TIREQ & Timer5) { process_timer5(); TIREQ = Timer5; } CREQ = TimerREQ; } Preliminary // If timer interrupt flag is set // Process Timer0 interrupt // Clear the flag of Timer0 // Process Timer0 interrupt // Clear the flag of Timer1 // Process Timer0 interrupt // Clear the flag of Timer2 // Process Timer0 interrupt // Clear the flag of Timer3 // Process Timer0 interrupt // Clear the flag of Timer4 // Process Timer0 interrupt // Clear the flag of Timer5 // Clear the flag of Timer
5-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTERRUPT CONTROLLER 0x80000100 18 17 16
CIF I2C ADC
Interrupt Enable Register (IEN) 31 30 29 28 27 26 25
Reserved
24 8
UB
23 7
UT
22 6
TC
21 5
I2T
20 4
I2R
19 3
E3
15
MEN
14
13
12
LCD
11
CDIF
10
UBH
9
GS
2
E2
1
E1
0
E0
TC32 DMA
MEN [15] Master Enable 0 All interrupts are disabled. 1 Any interrupt enabled by corresponding bit[18:0] can be generated to CPU *) Master Enable functionality is not effective if RDYIRQEN bit of Miscellaneous Configuration Register is set as "1". Bit Field CIF [18] I2C [17] ADC [16] RDY [15] TC32 [14] DMA [13] LCD [12] CDIF [11] UBH [10] GS [9] UB [8] UT [7] TC [6] I2T [5] I2R [4] E3 [3] E2 [2] E1 [1] E0 [0] Interrupt Request Control 1 = Interrupt enabled, 0 = Interrupt disabled Camera Interface interrupt control I2C interrupt control ADC interrupt control External Bus READY interrupt control. This bit is effective only when RDYIRQEN bit of Miscellaneous Configuration Register is set to high. 32-bit Timer interrupt control DMA interrupt control LCD interrupt control CDIF interrupt control USB Host interrupt control GSIO interrupt control USB interrupt control UART/IrDA interrupt control Timer/Counter interrupt control I2S TX interrupt control I2S RX interrupt control External interrupt request 3 control External interrupt request 2 control External interrupt request 1 control External interrupt request 0 control
Clear Interrupt Request Register (CREQ) 31 30 29 28 27 26 25 24 23
Reserved
22 6
TC
21 5
I2T
20 4
I2R
19 3
E3
0x80000104 18 17 16
CIF I2C ADC
15
RDY
14
TC32
13
DMA
12
LCD
11
CDIF
10
UBH
9
GS
8
UB
7
UT
2
E2
1
E1
0
E0
By writing "1" to each field, the interrupt request flag of corresponding interrupt is cleared. Writing to "0" doesn't mean anything and the corresponding flag remains its previous state. Interrupt Request Register (IREQ) 31 30 29 28 27 26 25
Reserved
24 8
UB
23 7
UT
22 6
TC
21 5
I2T
20 4
I2R
19 3
E3
0x80000108 18 17 16
CIF I2C ADC
15
RDY
14
13
12
LCD
11
CDIF
10
UBH
9
GS
2
E2
1
E1
0
E0
TC32 DMA
If each field is "1", it means that the corresponding interrupt has been requested. If each peripheral has its own request flags, it means at least one of those flags has been set.
Preliminary
5-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTERRUPT CONTROLLER
IRQ Interrupt Select Register (IRQSEL) 31 30 29 28 27 26 25 24
Reserved
23 7
UT
22 6
TC
21 5
I2T
20 4
I2R
19 3
E3
0x8000010C 18 17 16
CIF I2C ADC
15
RDY
14
13
12
LCD
11
CDIF
10
UBH
9
GS
8
UB
2
E2
1
E1
0
E0
TC32 DMA
If each field is "1", it means that the corresponding interrupt is considered as IRQ interrupt, if each field is `0' it means that its interrupt is considered as FIQ interrupt. Refer to chapter 3 for more information about IRQ / FIQ interrupts. External Interrupt Configuration Register (ICFG) 15 14 13 12 11 10 9 8 7 6
FE3 DTYPE3 FT3 FE2 DTYPE2 FT2 FE1
5
4
FT1
3
FE0
0x80000110 2 1 0
DTYPE0 FT0
DTYPE1
FE3~FE0 Filter Enable 0 Noise filter is enabled (in case of DTYPEn != 3) 1 Noise filter is disabled (in case of DTYPEn != 3) If DTYPEn == 3, noise filter is always enabled, and this field sets which level generates the interrupt. If it is set to 1, level high triggers interrupt, and if it is set to 0, level low triggers interrupt. DTYPE3~0 0 1 2 3 Detection Type Falling edge triggered external interrupt Rising edge triggered external interrupt Both edge triggered external interrupt Level high / low triggered external interrupt FEn field determines which level triggers the interrupt. If FEn == 1, level high triggers the interrupt and FEn == 0, level low triggers the interrupt. Filter Type Reserved
FT3~FT0 X
Following is the summary of all above fields. Table FEn, DTYPEn 000 001 010 011 100 101 110 111 5.2 Summary of External Triggering Set falling edge triggered Set rising edge triggered Set both edge triggered Set low level triggered Set falling edge triggered Set rising edge triggered Set both edge triggered Set high level triggered Interrupt Configuration Noise Filter Filter Enabled Filter Enabled Filter Enabled Filter Enabled Filter disabled Filter disabled Filter disabled Filter Enabled
"011" and "111" are recommended to avoid conflicts caused by the different interpretation between Wakup Event logic and Interrupt Generation logic. (Refer to "Wakeup Control Register" description).
Preliminary
5-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTERRUPT CONTROLLER
Masked Interrupt Request Register (MREQ) 31 30 29 28 27 26 25 24 23
Reserved
22 6
TC
21 5
I2T
20 4
I2R
19 3
E3
0x80000114 18 17 16
CIF I2C ADC
15
RDY
14
13
12
LCD
11
CDIF
10
UBH
9
GS
8
UB
7
UT
2
E2
1
E1
0
E0
TC32 DMA
Same meaning as IREQ except that it represents only that of the enabled interrupts. Only the flags of enabled interrupts can be checked by this register. It is recommended that use MREQ register instead of IREQ in the interrupt handler routine. Test Mode Register (TSTREQ) 31 30 29 28 27 26 15
RDY
25
Reserved
24 8
UB
23 7
UT
22 6
TC
21 5
I2T
20 4
I2R
19 3
0x80000118 18 17 16
CIF I2C ADC
14
13
12
LCD
11
CDIF
10
UBH
9
GS
2
1
0
TC32 DMA
Reserved
This register can be used to generate an interrupt by writing 1 at the corresponding bit of the internal interrupt source. This register is for testing purpose only. It must be remained zero during normal operation. IRQ Raw Status Register (IRQ) 31 30 29 28 27 26 25
Reserved
24 8
UB
23 7
UT
22 6
TC
21 5
I2T
20 4
I2R
19 3
E3
0x80000120 18 17 16
CIF I2C ADC
15
RDY
14
13
12
LCD
11
CDIF
10
UBH
9
GS
2
E2
1
E1
0
E0
TC32 DMA
This register reflects IREQ bits selected when the corresponding IRQSEL bit is low (IREQ & IRQSEL) FIQ Raw Status Register (FIQ) 31 30 29 28 27 26 25
Reserved
24 8
UB
23 7
UT
22 6
TC
21 5
I2T
20 4
I2R
19 3
E3
0x80000124 18 17 16
CIF I2C ADC
15
RDY
14
13
12
LCD
11
CDIF
10
UBH
9
GS
2
E2
1
E1
0
E0
TC32 DMA
This register reflects IREQ bits selected when corresponding IRQSEL bit is high (~IREQ & IRQSEL). Masked IRQ Raw Status Register (MIRQ) 31 30 29 28 27 26 25 24 23
Reserved
22 6
TC
21 5
I2T
20 4
I2R
19 3
E3
0x80000128 18 17 16
CIF I2C ADC
15
RDY
14
13
12
LCD
11
CDIF
10
UBH
9
GS
8
UB
7
UT
2
E2
1
E1
0
E0
TC32 DMA
MIRQ = IRQ & IEN Masked FIQ Raw Status Register (MFIQ) 31 30 29 28 27 26 25 24 23
Reserved
22 6
TC
21 5
I2T
20 4
I2R
19 3
E3
0x8000012C 18 17 16
CIF I2C ADC
15
RDY
14
13
12
LCD
11
CDIF
10
UBH
9
GS
8
UB
7
UT
2
E2
1
E1
0
E0
TC32 DMA
MFIQ = FIQ & IEN
Preliminary
5-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 INTERRUPT CONTROLLER 0x80000130 18 17 16
CIF I2C ADC
Trigger Mode Register (TMODE) 31 30 29 28 27 26 25
Reserved
24 8
UB
23 7
UT
22 6
TC
21 5
I2T
20 4
I2R
19 3
15
RDY
14
13
12
LCD
11
CDIF
10
UBH
9
GS
2
1
0
TC32 DMA
Reserved
This register selects trigger mode (0: edge, 1:level) for each internal interrupt source. Synchronization Control Register (SYNC) 31 30 29 28 27 26 25 24 23
Reserved
22 6
TC
21 5
I2T
20 4
I2R
19 3
0x80000134 18 17 16
CIF I2C ADC
15
RDY
14
13
12
LCD
11
CDIF
10
UBH
9
GS
8
UB
7
UT
2
1
0
TC32 DMA
Reserved
By default, all internal interrupt source lines are synchronized to HCLK. This register disables synchronization registers (0: sync enabled, 1:sync disabled). Do not disable synchronization if an interrupt source is asynchronous to HCLK Wakeup Control Register (WKUP) 31 30 29 28 27 26 25
Reserved
24 8
UB
23 7
UT
22 6
TC
21 5
I2T
20 4
I2R
19 3
E3
0x80000138 18 17 16
CIF I2C ADC
15
RDY
14
13
12
LCD
11
CDIF
10
UBH
9
GS
2
E2
1
E1
0
E0
TC32 DMA
This register enables each interrupt source to be used as an asynchronous wakup event for Power Down or IDLE mode. By default, all interrupt source lines are used for system wakeup events in power down mode. (0: enabled, 1: disabled). Appropriate bits must be enabled before the system enters power down mode (clock stop mode). Otherwise, system cannot wakeup. Refer to section "Power Down Mode" and "IDLE mode" in Chapter "Clock Generator".
Before enable E3 ~ E0 (external interrupt pins), FE3 ~ FE0 bits of ICFG register must be changed to control the polarity of each external interrupt pin. In wakup event control logic, FE3 ~ FE0 bits of ICFG are used as polarity control bits for the external interrupt pins ("0" indicates active low, "1" indicates active high). Watch out for the different interpretation of ICFG register between two logics.
Table 5.3 ICFG Usage for WakeUp Event
FEn, DTYPEn of ICFG Register 000 001 010 011 100 101 110 111 Interrupt Generation Logic Triggering Noise Filter Falling edge triggered Filter enabled Rising edge triggered Filter enabled Both edge triggered Filter enabled Low level triggered Filter enabled Falling edge triggered Filter disabled Rising edge triggered Filter disabled Both edge triggered Filter disabled High level triggered Filter enabled WakeUp Event Control Logic
Low level trigger, filter disabled
High level trigger, filter disabled
As long as the HCLK is alive, any interrupt source lines with the corresponding Interrupt Enable bit active can wakeup the system from Power Down or IDLE Mode. (The TCC76x Clock Generator also accepts nIRQ and nFIQ for wakeup). But when the HCLK is stopped, the Interrupt Controller is stopped also, and no event output is generated to the clock generation logic. Thus, the system can never be woke up if Wakup Control Register is not used at all. Wakeup Control Register must be used in Power Down or IDLE Mode if the HCLK is to be disabled. It is recommended to disable Interrupt Enable Register if Wakeup Control Register bits are used.
Preliminary
5-6
TCC76x
6 TIMER / COUNTER 6.1 Overview
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TIMER / COUNTER
The TCC76x has four 16bit and two 20bit timer/counters. Each timer counter has three registers for basic operation modes. Refer to register description table for details. When operating in counter modes, External interrupt pin is used as counting clock for that counter. The main clock frequency of timer counter can be configured by setting TCLK frequency. (Refer to Clock generator block) With the 12bit internal basic counter, the timer counter can generate various intervals from microseconds to seconds unit. In addition to TCC72x compatible timers/counters, the TCC76x provides a 32-bit general-purpose up counter. (Refer to Figure 6.3). The following figure represents the block diagram of timer/counter.
external clock source through the noise filter of interrupt controller
pi_EXTCK<3:0>
TCLK
Basic Counter
Clock Selector
Counter
TCFG APB TCNT TREF Compare (=)
TREQ
TMREF
Compare (=) Tgl TCO
Figure 6.1 Timer Counter Block Diagram The following table explains the registers of each timer counter. The address of each timer counter is 16bytes aligned. The base address of timer counter is 0x80000200. The number n represents for each timer/counter. In case of timer/counter 4, 5 (that is n = 4 or 5) the TREF, TCNT register has 20bit resolution. It can be used for generating long time of event.
Preliminary
6-1
TCC76x
6.2 Register Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TIMER / COUNTER
Name TCFG0 TCNT0 TREF0 TMREF0 TCFG1 TCNT1 TREF1 TMREF1 TCFG2 TCNT2 TREF2 TMREF2 TCFG3 TCNT3 TREF3 TMREF3 TCFG4 TCNT4 TREF4 TCFG5 TCNT5 TREF5 TIREQ TWDCFG TWDCLR TC32EN TC32LDV TC32CMP0 TC32CMP1 TC32PCNT TC32MCNT TC32IRQ
Table 6.1 Timer/Counter Register Map (Base Address = 0x80000200) Address Type Reset Description 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x0050 0x0054 0x0058 0x0060 0x0070 0x0074 0x0080 0x0084 0x0088 0x008C 0x0090 0x0094 0x0098 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W R/W R/W R/W R/W R/W R/W R/W 0x00 0x0000 0xFFFF 0x0000 0x00 0x0000 0xFFFF 0x0000 0x00 0x0000 0xFFFF 0x0000 0x00 0x0000 0xFFFF 0x0000 0x00 0x00000 0xFFFFF 0x00 0x00000 0xFFFFF 0x0000 0x0000 0x00007FFF 0x00000000 0x00000000 0x00000000 0x0000---Timer/Counter 0 Configuration Register Timer/Counter 0 Counter Register Timer/Counter 0 Reference Register Timer/Counter 0 Middle Reference Register Timer/Counter 1 Configuration Register Timer/Counter 1 Counter Register Timer/Counter 1 Reference Register Timer/Counter 1 Middle Reference Register Timer/Counter 2 Configuration Register Timer/Counter 2 Counter Register Timer/Counter 2 Reference Register Timer/Counter 2 Middle Reference Register Timer/Counter 3 Configuration Register Timer/Counter 3 Counter Register Timer/Counter 3 Reference Register Timer/Counter 3 Middle Reference Register Timer/Counter 4 Configuration Register Timer/Counter 4 Counter Register Timer/Counter 4 Reference Register Timer/Counter 5 Configuration Register Timer/Counter 5 Counter Register Timer/Counter 5 Reference Register Timer/Counter n Interrupt Request Register Watchdog Timer Configuration Register Watchdog Timer Clear Register 32-bit Counter Enable / Pre-scale Value 32-bit Counter Load Value 32-bit Counter Match Value 0 32-bit Counter Match Value 1 32-bit Counter Current Value (pre-scale counter) 32-bit Counter Current Value (main counter) 32-bit Counter Interrupt Control
Preliminary
6-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TIMER / COUNTER 0x80000200 + (0x10 * n) 4 3 2 1 0
IEN PWM CON EN
Timer/Counter n Configuration Register (TCFGn) 15 14 13 12 11 10 9 8 7 6
0 CC POL
5
TCKSEL
CC [8] 0 1 POL 0 1
[7]
Clear Count TCNTn is not cleared. TCNTn is cleared to zero. TCK Polarity TCNTn is incremented at rising edge of the selected counting clock TCNTn is incremented at falling edge of the selected counting clock TCK Select TCK is internally generated from divider circuit. It is driven by TCLK, and this value determines the division factor of this circuit. Division factor is 2(k+1). TCK is internally generated from divider circuit. It is driven by TCLK, and this value determines the division factor of this circuit. Division factor is 22k TCK is the external pin shared by external interrupt signal. In the TCC76x, there are 4 external pins for this purpose, so this configuration is valid only for timer/counter 3 ~ 0. (not for timer/counter 5, 4) Interrupt Enable Enable Timer/Counter interrupt Disable Timer/Counter interrupt PWM Mode Enable Enable PWM mode Timer/Counter output is changed at every time the TCNTn is equal to TREFn and TMREFn value. It can be used to generate PWM waveform, by changing TMREFn while fixing TREFn. (where, TREFn > TMREFn) Disable PWM mode Timer/Counter output can be changed only when the TCNTn is equal to TREFn. It can be used to generate a rectangular pulse of variable frequency.
TCKSEL
[6:4]
k=0~4
k = 5, 6
k=7
IEN [3] 1 0 PWM
[2]
1
0
The output of 6 Timer/Counters can be monitored through GPIO_A ports. Refer to GPIO chapter for more information. CON 0 1 EN [0] 1
[1]
Continue Counting When the TCNTn is reached to TREFn, TCNTn restarts counting from 0 at the next pulse of selected clock source. The TCNTn continues counting from the TREFn. Timer/Counter Enable Timer counter is enabled.
Preliminary
6-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TIMER / COUNTER
Following figure illustrates the basic behavior of timer / counter.
CONT= 1, IEN = 1 , PWM = 0 , TCKSEL= 0, TREF= 3 TCLK TCK TCNT TEQU TCO nTREQ CONT = 0 , IEN = 1, PWM = 1, TCKSEL= 0 , TREF= 3 , TMREF= 1 TCLK TCK TCNT TMEQU TEQU TCO nTREQ 0 1 2 3 0 1 2 TCO TCO is inverted 0 1 2 3 4 5 6
Figure 6.2 Timing diagram of timer/counter
Timer/Counter n Counting Register (TCNTn) 31 30 29 28 27 26 25 24 23
0
22 6
21 5
0x80000204 + (0x10 * n) 20 19 18 17 16
TCNTn[19:16]
15
14
13
12
11
10
9
8
7
4
3
2
1
0
TCNTn[15:0]
TCNTn is increased by 1 at every pulse of selected clock source. TCNTn can be set to any value by writing to this register. In case of timer 4 and timer 5, it has 20 bits, otherwise it has 16 bits. Timer/Counter n Counting Reference Register (TREFn) 0x80000208 + (0x10 * n) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 TREFn[19:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TREFn[15:0]
When TCNTn is reached at TREFn and the CON flag of TCFGn register is set to 1, the TCNTn is cleared to 0 at the next pulse of selected clock source. According to the TCFGn settings, various kinds of operations may be done. In case of timer 4 and timer 5, it has 20 bit, otherwise it has 16 bit.
Preliminary
6-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TIMER / COUNTER
Timer/Counter n Middle Reference Register (TMREFn) 0x8000020C + (0x10 * n) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 TMREFn[19:16]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
TMREFn[15:0]
When TCNTn is reached at TMREFn and the PWM flag of TCFGn register is set to 1, the timer output of TCOn is cleared to 0 at the negative edge of that pulse of selected clock source. The TCOn is set to 1 when the TCNTn is reached at TREFn. (refer Figure 6.1). So you can generate PWM signal by modifying TMREFn between 0 ~ (TREFn-1). In case of timer 4 and timer 5, it has 20 bit, otherwise it has 16 bit. Timer/Counter Interrupt Request Register (TIREQ) 15 14 13 12 11 10 9 8 7 6
0 TWF TF5 TF4 TF3 TF2
[14]
TF1
TF0
0
TWI
5 TI5
4 TI4
3 TI3
0x80000260 2 1 0 TI2 TI1 TI0
TWF 1 TFn
Watchdog Timer Flag Watchdog timer has reached to its reference value. Timer/Counter n Flag Timer/counter n has reached to its reference value. Type Read Write Type Read Write Watchdog Timer Interrupt Request Flag Watchdog timer has generated its interrupt. Watchdog timer interrupt is cleared. Timer/Counter n Interrupt Request Flag Timer/counter n has generated its interrupt. Timer/counter n interrupt flag is cleared.
[13:8]
1 TWI [6] 1 1 TIn [5:0] 1 1
If a timer n has reached its reference value, the TFn is set. (bit n represents for Timer n). If its interrupt request is enabled by set bit 3 of TCFGn register, then the TIn is set. If the TC bit of IEN register is set, the timer interrupt is really generated and this TIREQ register can be used to determine which timer has requested the interrupt. After checking these flags, user can clear these TFn and TIn field by writing "1" to corresponding TFn or TIn bit field.
Preliminary
6-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TIMER / COUNTER 0x80000270 2 1 0
0 ISEL EN
Watchdog Timer Configuration Register (TWDCFG) 15 14 13 12 11 10 9 8 7 6
0
5
TCKSEL
4
3
IEN
Watchdog timer is used for the system not to be stuck by generating a reset pulse or interrupt automatically when the watchdog timer counter overflows to zero. The programmer must clear the watchdog counter before it overflows by writing any value to TWDCLR register. The duration can be chosen by selecting TCKSEL field appropriately. TCKSEL
[6:4]
TCK Select Undefined. Should not be used. TCK is internally generated from divider circuit. It is driven by TCLK, and this value determines the division factor of this circuit. Division factor is 25. TCK is internally generated from divider circuit. It is driven by TCLK, and this value determines the division factor of this circuit. Division factor is 22k Undefined. Should not be used. Interrupt Enable Watchdog Timer Interrupt is enabled. This field is valid only if RST field is set to 0.
k=0~3 k=4 k = 5, 6 k=7 IEN 1 ISEL 0 1 EN
[0] [1] [3]
Interrupt Select Watchdog timer generates the reset signal when it reaches to the reference value, the reset signal is applied to every component in the chip. Watchdog timer does not generate reset signal although it reaches to the reference value, and it continue counting from 0. Watchdog Timer Enable Watchdog timer is enabled. If the watchdog timer is disabled, its counter goes to 0xE0, so when it is first enabled, user must clear the counter by writing to TWDCLR register. 0x80000274 2 1 0
1
Watchdog Timer Clear Register (TWDCLR) 15 14 13 12 11 10 9 8 7
any value
6
5
4
3
The watchdog timer counter can be cleared to 0 by writing any value to this register. If it is not cleared before it overflows, the watchdog timer generate reset signal to the entire component of chip.
Preliminary
6-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TIMER / COUNTER
As illustrated in the figure below, TC32 consists of a pre-scale counter, main counter and two comparators. The pre-scale counter is a simple 24-bit up-counter which always counts from zero to PRESCALE value programmed in TC32EN register. The 32-bit main counter is incremented only when the prescale counter reaches PRESCALE value. The clock input of TC32 module can be either XTIN (default) or XIN. Refer to Clock Generator description (XTTC32 bit of PWDCTL register).
ZCLK from Clock Controller (XTIN or XIN) TC32EN Pre-scale Counter
APB
TC32LDV TC32CMP0
Main Counter Compare (=) Compare (=)
TC32CMP1
IRQ Sync.
IRQ to Interrupt Controller
TC32IRQ
Figure 6.3 32-bit Counter Block Diagram
Possible counter modes are described in the table below. Table 6.2 TC32 Count Mode
Mode 0 1 2 3 4 5 6 7 TC32EN Register Bits LOADZERO 0 0 0 0 1 1 1 1 LDM1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Main Counter Operation End Count Value 0xFFFFFFFF CMP0 (if LOADVAL < CMP0) CMP1 (if LOADVAL < CMP1) CMP0 (if LOADVAL < CMP0 CMP1) or CMP1 (if LOADVAL < CMP1 CMP0) 0 0 0 0 LOADVAL - 1 CMP0 (if LOADVAL > CMP0) CMP1 (if LOADVAL > CMP1) CMP0 (if LOADVAL > CMP1 CMP0) or CMP1 (if LOADVAL > CMP0 CMP1) Refer to register descriptions below for CMP0, CMP1 and LOADVAL. Mode0 can be used as 1Hz counter mode, if PRESCALE = 0x007FFF, STOPMODE = 0, ZCLK = XTIN(32.768kHz) LOADVAL LOADVAL LOADVAL LOADVAL LDM0 Start Count Value
Preliminary
6-7
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TIMER / COUNTER
TC32 Enable / Pre-scale Value Register (TC32EN)
Bit 31:30 29 28 27 26 25 24 23:0 Name Reserved LDM1 LDM0 Reserved STOPMODE LOADZERO ENABLE PRESCALE Default 0 0 0 0 0 0 0 0x007FFF R/W R R/W R/W R R/W R/W R/W R/W Description
0x80000280
Re-load counter when the counter value matched with CMP1. LOADZERO bit below selects the couter load(start) value. Re-load counter when the counter value matched with CMP0 LOADZERO bit below selects the couter load(start) value. 0 = Free Running Mode, 1 = Stop Mode. By default, counter starts from LOADVAL. When this bit is enabled (1), the counter is forced to count from "0" to "LOADVAL - 1". Counter Enable Pre-scale counter load value. The pre-scale counter always runs from "0" up to PRESCALE. The default value is for 1Hz counter when ZCLK = XTIN (32.768kHz).
TC32 Load Value Register (TC32LDV)
Bit Name Default R/W Description 31: 0 LOADVAL 0x00000000 R/W Counter Load Value. The counter is restarted whenenver one of the TC32En and TC32LDV is written.
0x80000284
TC32 Match Value 0 Register (TC32CMP0)
Bit 31: 0 Name CMP0 Default 0x00000000 R/W R/W Description Counter Match Value
0x80000288
TC32 Match Value 1 Register (TC32CMP1)
Bit 31: 0 Name CMP1 Default 0x00000000 R/W R/W Description Counter Match Value
0x8000028C
TC32 Pre-scale Counter Current Value Register (TC32PCNT)
Bit 31:24 23: 0 Name Reserved PCNT Default 0x00 0x000000 R/W R R Description
0x80000290
Pre-scale counter current value. The AHB system clock must be three times faster than the frequency of ZCLK to read valid value.
TC32 Main Counter Current Value Register (TC32MCNT)
Bit 31: 0 Name MCNT Default 0x00000000 R/W R
0x80000294
Description Main counter current value. When RSYNC is enabled, the AHB system clock must be faster than the frequency calculated below. (ZCLK frequency) / (PRESCALE + 1) * 3
TC32 Interrupt Control Register (TC32IRQ)
Bit 31 Name IRQCLR Default 0 R/W R/W
0x80000298
30 29:24
RSYNC BITSEL
0 0x00
R/W R/W
Description Interrupt Clear Control. When this bit is 0, interrupt status bits (IRQRSTAT) are cleared by reading this register. When this bit is set, IRQSTAT bits are cleared only if written with non-zero value. Synchronization control for Counter Current Value Registers (TC32PCNT and TC32MCNT). 0 = Enable, 1 = Disable. Counter bit selection value for interrupt generation. Any one of the counter bits {MCNT[31:0], PCNT[23:0]} selected by BITSEL is used to generate an interrupt. 0x00 ~ 0x17 : PCNT[0] ~ PCNT[23] 0x18 ~ 0x38: MCNT[0] ~ MCNT[31]
Preliminary
6-8
TCC76x
23:21 20 19 18 17 16 15:13 12:8 7:5 4:0 Reserved IRQEN[4] IRQEN[3] IRQEN[2] IRQEN[1] IRQEN[0] Reserved IRQRSTAT Reserved IRQMSTAT 0 0 0 0 0 0 0 0x00 0 0x00 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TIMER / COUNTER
Enable Interrupt at the rising edge of a counter bit selected by BITSEL. Enable Interrupt at the end of pre-scale count Enable Interrupt at the end of count Enable Interrupt when the counter value matched with CMP1 Enable Interrupt when the counter value matched with CMP0 Interrupt Raw Status. Refer to the description for IRQEN above. Masked Interrupt Status = IRQRSTAT & IRQEN
Preliminary
6-9
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TIMER / COUNTER
Preliminary
6-10
TCC76x
7 GPIO PORT 7.1 Overview
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GPIO PORT
The TCC76x has a lot of general purpose I/Os that can be programmed by setting internal registers. All I/Os are set to input mode at reset. Except for GPIO_B[29:26] (USB transceiver I/Os), all pins named with GPIO have the following features. - Programmable internal pull-up resistor - Programmable drive strength control (4/6/8/12mA) for output mode - Programmable I/O direction control
G IO C O N C ontrol of other block C ontrol of test or other block
0 MUX 1 2
P ull-up resistor c on trol fro m C F G P U x register
O utp u t o f tes t o r other block O utput of other b lo c k W rite APB GDATA
2 MUX 1 0 G P IO pin
1 MUX R ead G D A T A
G S E L, G T S E L
0
Figure 7.1 GPIO Block Diagram The I/O mode can be set by the state of GIOCON register. If a bit of GIOCON register is 1, the corresponding GPIO pin has come to output mode, and if 0, which is the default state of GIOCON register, the corresponding GPIO pin is set to input mode. If GPIO pin is set to input mode, GPIO pin's state can be fed to CPU by reading GDATA register and when output mode, GPIO pin's state can be controlled by the state of the corresponding bit of GDATA register. If GDATA register is read when the mode is output mode, the value that CPU gets is the one that CPU has written before. In the TCC76x, there are various kinds of peripherals that generate its own control signals. These peripherals can occupy the dedicated GPIO pins. This option is controlled by the state of the GSEL and GTSEL register. If a bit of these GSEL or GTSEL is 1, the corresponding GPIO pin is entered to other function mode, so used by other peripherals not by GPIO block. The direction control method of GPIO pins in the other function mode is determined case by case. One of them follows the normal direction control method using GIOCON register, the other method uses a its own direction control signals. For drive strength and internal pull-up resistor control, refer to section 12.2 Miscellaneous Register Description.
Preliminary
7-1
TCC76x
7.2 Register Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GPIO PORT
Name GDATA_A GIOCON_A GSEL_A GTSEL_A GDATA_B GIOCON_B GSEL_B GTSEL_B GDATA_C GIOCON_C GDATA_D GIOCON_D
Table 7.1 GPIO Register Map (Base Address = 0x80000300) Addr Type Reset Description 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x30 0x34 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0xFFFFFFFF 0x00000000 0x00000000 0x00000000 0x3FFFFFFF 0x000000FF 0x3C0000FF 0x00000000 0xFFFF 0x0000 0x007FFF 0x000000 GPIO_A Data Register GPIO_A Direction Control Register GPIO_A Function Select Register 1 GPIO_A Function Select Register 2 GPIO_B Data Register GPIO_B Direction Control Register GPIO_B Function Select Register 1 GPIO_B Function Select Register 2 GPIO_C Data Register GPIO_C Direction Control Register GPIO_D Data Register GPIO_D Direction Control Register
Reset values are valid only for the TCC761. All the other derivatives of the TCC76x may have different reset values. For those bits without external pins, reset values should not be changed. Read-modify-write sequence is recommended for all the GPIO registers
Special GPIO pins
A special GPIO register (MCFG register) exists in Memory controller. It can control MODE0(READY) pin and SD_CLK pin as general purpose input and output pin each other. That is, by setting appropriate field of MCFG register, user can monitor the state of MODE0(READY) pin and can manipulate the state of SD_CLK pin as low or high. Refer to Chapter 15 for more information of MCFG register.
GPIO_A Data Register (GDATA_A) 31 30 29 28 27 26 25 24 23 22 21 Data for GPIO_A[31:16] pin 15 14 13 12 11 10 9 8 7 6 5 Data for GPIO_A[15:0] pin
20 4
19 3
0x80000300 18 17 16 2 1 0
If a certain GPIO_A pin is set to output mode and act as GPIO, the corresponding bit of this register controls the status of GPIO_A pin; Low or High. If it is set to input mode and act as GPIO, the corresponding bit represents the status of GPIO_A pin; Low or High. GPIO_A Direction Control Register (GIOCON_A) 31 30 29 28 27 26 25 24 23 22 21 Direction control for GPIO_A[31:16] pin 15 14 13 12 11 10 9 8 7 6 5 Direction control for GPIO_A[15:0] pin 0x80000304 18 17 16 2 1 0
20 4
19 3
If a bit is set to 1, the corresponding GPIO_A pin is set to output mode. If set to 0, the corresponding GPIO_A pin is set to input mode.
Preliminary
7-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GPIO PORT 0x80000308 18 17 16 2 1 0 GS0[2:0]
GPIO_A Function Select Register (GSEL_A) 31 30 29 28 27 26 25 24 23 PD[15:0] 15 14 13 12 11 10 9 8 7 0 GS2[2:0] -
22 6
21
20
19 3 -
5 4 GS1[2:0]
If a bit is set to 1, the corresponding GPIO_A pin is used by the other dedicated peripherals. The dedicated peripherals for these GPIO_A pins are LCD controller, and three of four GSIO ports. PD[15:0] GPIO_A[31:16] Function Select 0 GPIO_A[31:16] pin is working as Normal GPIO Function if bit n = 1 GPIO_A[n+16] : Pixel Data[n] of LCD block *These fields are valid only in TCC761. GSn[2:0] GPIO_A[10:8], GPIO_A[6:4], GPIO_A[2:0] Function GPIO_A[10:8], GPIO_A[6:4], GPIO_A[2:0] pin is working as Normal 0 GPIO Function GS2[2] = 1 GPIO_A[10] : FRM signal of GSIO2 block GS2[1] = 1 GPIO_A[ 9] : SCK signal of GSIO2 block GS2[0] = 1 GPIO_A[ 8] : SDO signal of GSIO2 block GS1[2] = 1 GPIO_A[ 6] : FRM signal of GSIO1 block GS1[1] = 1 GPIO_A[ 5] : SCK signal of GSIO1 block GS1[0] = 1 GPIO_A[ 4] : SDO signal of GSIO1 block GS0[2] = 1 GPIO_A[ 2] : FRM signal of GSIO0 block GS0[1] = 1 GPIO_A[ 1] : SCK signal of GSIO0 block GS0[0] = 1 GPIO_A[ 0] : SDO signal of GSIO0 block SDI signal for GSIO2, GSIO1, GSIO0 block is always fed through GSIO_A[11], GSIO_A[7], GSIO_A[3] pin regardless of these GS[2:0] bit. But to use GSIO, these pins must be set to input mode ahead. GPIO_A Test Select Register (GTSEL_A) 31 30 29 28 27 26 25 24 0 15 14 0 13 12 11 TC2 10 9 EX2CLK 8 TC5 7 TC1 6 0 5 4 TC4 3 TC0 2 0 1 0 TC3 0x8000030C 18 17 16
23
22
21
20
19
If a bit is set to 1, and the corresponding bit of GSEL_A is 0, GPIO_A pin is used by the other dedicated peripherals. It is used to set the output of timer TC5 ~ TC0 GPIO_A[11,8,7,4,3,0] Function Select 0 GPIO_A[11,8,7,4,3,0] pin is working as Normal GPIO Function 1 GPIO_A[11,8,7,4,3,0] is the output of six timer/counters *) These fields are valid only if the corresponding bit of GSEL_A is set to 0
Preliminary
7-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GPIO PORT 0x80000310 18 17 16 2 1 0
GPIO_B Data Register (GDATA_B) 31 30 29 28 27 26 25 24 23 22 21 20 0 Data for GPIO_B[29:16] pin 15 14 13 12 11 10 9 8 7 6 5 4 Data for GPIO_B[15:0] pin
19 3
If a certain GPIO_B pin is set to output mode and act as GPIO, the corresponding bit of this register controls the status of GPIO_B pin; Low or High. If it is set to input mode and act as GPIO, the corresponding bit represents the status of GPIO_B pin; Low or High. GPIO_B Direction Control Register (GIOCON_B) 31 30 29 28 27 26 25 24 23 22 21 20 0 Direction control for GPIO_B[29:16] pin 15 14 13 12 11 10 9 8 7 6 5 4 Direction control for GPIO_B[15:0] pin 0x80000314 18 17 16 2 1 0
19 3
If a bit is set to 1, the corresponding GPIO_B pin is set to output mode. If set to 0, GPIO_B pin is set to input mode. The GPIO_B[29:28] and GPIO_B[27:26] pin is unable to be set to different I/O mode. That is, GPIO_B[29] have always same direction with GPIO_B[28], and it is same for GPIO_B[27] and GPIO_B[26]. So to make GPIO_B[29:28] or GPIO_B[27:26] output port you must set both GIOCON_B[29] and GIOCON_B[28] to 1 or both GPIO_B[27] and GPIO_B[26] to 1 concurrently. GPIO_B Function Select Register (GSEL_B) 31 30 29 28 27 26 25 24 23 22 0 USBH[1:0] USB[1:0] 0 DAI[3:0] 15 14 13 12 11 10 9 8 7 6 0 GS3[2:0] 0 UTX NWE IDE 0x80000318 20 19 18 17 16 LCD[3:0] 0 4 3 2 1 0 CS[3:0] SCS CKE
21 5
If a bit is set to 1, the corresponding GPIO_B pin is used by the other dedicated peripherals. The dedicated peripherals for these GPIO_B pins are USB controller, DAI & CDIF controller., UART, memory controller, and one of four GSIO ports. USBH
[29:28]
0 3 USB
[27:26]
GPIO_B[29:28] Function Select GPIO_B[29:28] pin is working as Normal GPIO Function GPIO_B[29:28] pin are working as USBH D- / D+ Port GPIO_B[27:26] Function Select GPIO_B[27:26] pin is working as Normal GPIO Function GPIO_B[27:26] pin are working as USB D- / D+ Port GPIO_B[24:21] Function Select GPIO_B[24:21] pin is working as Normal GPIO Function GPIO_B[24] pin is working as DAO signal of DAI block GPIO_B[23] pin is working as MCLK signal of DAI block GPIO_B[22] pin is working as LRCK signal of DAI block GPIO_B[21] pin is working as BCLK signal of DAI block
0 3 DAI
[24:21]
0 DAI[3] = 1 DAI[2] = 1 DAI[1] = 1 DAI[0] = 1
Preliminary
7-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GPIO PORT
LCD
[20:17]
0 LCD[3] = 1 LCD[2] = 1 LCD[1] = 1 LCD[0] = 1
GPIO_B[20:17] Function Select GPIO_B[20:17] pin is working as Normal GPIO Function GPIO_B[20] pin is working as AC_BIAS of LCD block GPIO_B[19] pin is working as PXCLK of LCD block GPIO_B[18] pin is working as VSYNC of LCD block GPIO_B[17] pin is working as HSYNC of LCD block
* These fields are valid only in TCC761. GS3
[12:10]
0 GS3[2] = 1 GS3[1] = 1 GS3[0] = 1
GPIO_B[12:10] Function Select GPIO_B[12:10] pin is working as Normal GPIO Function GPIO_B[12] pin is working as FRM of GSIO3 block GPIO_B[11] pin is working as SCK of GSIO3 block GPIO_B[10] pin is working as SDO of GSIO3 block
* These fields are valid only in TCC761. UTX 0 1 NWE 0 1
[7] [8]
GPIO_B[8] Function Select GPIO_B[8] pin is working as Normal GPIO Function GPIO_B[8] : UART TX signal of UART block GPIO_B[7] Function Select GPIO_B[7] pin is working as Normal GPIO Function GPIO_B[7] : ND_nWE (write enable for NAND flash) GPIO_B[6] Function Select GPIO_B[6] pin is working as Normal GPIO Function
IDE [6] 0
1 GPIO_B[6] : IDE_nCS1 (chip select for IDE device) * These fields are valid only in TCC761. CS
[5:2]
0 CS[3] = 1 CS[2] = 1 CS[1] = 1 CS[0] = 1 SCS [1] 0 1 CKE [0] 0 1
GPIO_B[5:2] Function Select GPIO_B[5:2] pin is working as Normal GPIO Function GPIO_B[5] : nCS3 or ND_nOE3 of memory controller GPIO_B[4] : nCS2 or ND_nOE2 of memory controller GPIO_B[3] : nCS1 or ND_nOE1 of memory controller GPIO_B[2] : nCS0 or ND_nOE0 of memory controller GPIO_B[1] Function Select GPIO_B[1] pin is working as Normal GPIO Function GPIO_B[1] : SD_nCS (chip select for SDRAM) GPIO_B[0] Function Select GPIO_B[0] pin is working as Normal GPIO Function GPIO_B[0] : SD_CKE (clock enable for SDRAM)
Preliminary
7-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GPIO PORT 0x8000031C 18 17 16 0 2 1 0 0 FOUT
GPIO_B Test Select Register (GTSEL_B) 31 30 29 28 27 26 25 24 EX1A EX2 EX1B 0 0 15 14 13 12 11 10 9 8 0 IDECS
23
22 21 GST[2:0] 7 6 5 0
20
19
4 3 EX1CLK
If a bit is set to 1, and the corresponding bit of GSEL_B is 0, GPIO_B pin is used by the other dedicated peripherals. EX1A 0 1
[29]
GPIO_B[29] Function Select GPIO_B[29] pin is working as Normal GPIO Function or USB DN GPIO_B[29] pin is working as EX1CLK from Clock Controller GPIO_B[28] Function Select GPIO_B[28] pin is working as Normal GPIO Function or USB DP GPIO_B[28] pin is working as EX2CLK from Clock Controller GPIO_B[24] Function Select GPIO_B[24] pin is working as Normal GPIO Function or I2S Data Output GPIO_B[24] pin is working as EX1CLK from Clock Controller GPIO_B[23:21] Function Select GPIO_B[23:21] pin is working as Normal GPIO Function GPIO_B[23] pin is working as FRM of 1 of 4 GSIO blocks GPIO_B[22] pin is working as SCK of 1 of 4 GSIO blocks GPIO_B[21] pin is working as SDO of 1 of 4 GSIO blocks GPIO_B[9] Function Select GPIO_B[9] pin is working as Normal GPIO Function GPIO_B[9] pin is working as IDE_nCS1 GPIO_B[5:2] Function Select GPIO_B[5:2] pin is working as Normal GPIO Function GPIO_B[5:2] pin is working as EX1CLK from Clock Controller
EX2 [28] 0 1 EX1A 0 1 GST
[23:21] [24]
0 GST[2] = 1 GST[1] = 1 GST[0] = 1 IDECS 0 1
[9]
EX1CLK
[5:2]
0 1 FOUT 0 1
[0]
GPIO_B[0] Function Select GPIO_B[0] pin is working as Normal GPIO Function GPIO_B[0] pin is working as FOUT from Clock Controller
Preliminary
7-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GPIO PORT 0x80000320 18 17 16 2 1 0
GPIO_C Data Register (GDATA_C) 31 30 29 28 27 26 25 15 14 13 12 11 10
24 0
23
22
21 5
20 4
19 3
9 8 7 6 Data for GPIO_C[15:0] pin * This register is valid only in TCC761.
If a certain GPIO_C pin is set to output mode and act as GPIO, the corresponding bit of this register controls the status of GPIO_C pin; Low or High. If it is set to input mode and act as GPIO, the corresponding bit represents the status of GPIO_C pin; Low or High. GPIO_C Direction Control Register (GIOCON_C) 31 30 29 28 27 26 25 24 23 22 21 0 15 14 13 12 11 10 9 8 7 6 5 Direction control for GPIO_C[15:0] pin * This register is valid only in TCC761. 0x80000324 18 17 16 2 1 0
20 4
19 3
If a bit is set to 1, the corresponding GPIO pin is set to output mode. GPIO_C port works only in 16-bit bus mode. In 32-bit bus mode, this port works as an upper half bus of 32-bit data bus. GPIO_D Data Register (GDATA_D) 0x80000330 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 Data for GPIO_D[21:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data for GPIO_D[15:0] pins (Bits [14:0] are valid only in TCC761) GPIO_D Direction Control Register (GIOCON_D) 0x80000334 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 Direction Control for GPIO_D[21:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Direction control for GPIO_D[15:0] pin (Bits [14:0] are valid only in TCC761) * At power on reset, internal pull-up resistors are enabled for GPIO_D[21:18] pins. If a bit is set to 1, the corresponding GPIO_D pin is set to output mode. If set to 0, GPIO_D pin is set to input mode.
Preliminary
7-7
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GPIO PORT
Preliminary
7-8
TCC76x
8 CLOCK GENERATOR 8.1 Overview
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR
The TCC76x has a lot of peripherals with different operating frequency. To provide an appropriate clock to each peripheral, the TCC76x has a clock generator unit. There is also a power management feature that can manage several operating modes, such as initialization mode, normal operation mode, idle mode, stop mode.
PWRDN XIN PLLmode
WAITGEN PLL
PLLDIVCLK
i_XIN WAIT PLLOUT
[18]
XTIN
MUX
PWDCTL[17]
Divider FCLK GEN
PWDCTL[9:8]
MUX MUX
PWDCTL[16]
DIVCLK0
SCLKmode[5:0]
FCLK (CPU)
MUX
DIVCLK1
SCLKmode[13:8]
HCLK GEN
HCLK (AHB)
MUX
[15:14]
DCLKmode
DCLK GEN EX1CLK GEN EX2CLK GEN UTCLK GEN USBCLK GEN LCLK GEN
DCLK (GSIO)
MUX
[15:14]
EX1CLKmode
EX1CLK (External)
MUX
[15:14]
EX2CLKmode
EX2CLK (I2C)
MUX
[15:14]
UTCLKmode
UTCLK (UART) UHCLK (USB Host) UDCLK (USB Device) LCLK (LCD)
MUX
[9:8]
UBCLKmode
MUX
[9:8]
PXCLKmode
MUX
[9:8]
TCLKmode
TCLK GEN
TCLK (Timer/Counter)
MUX
[9:8]
GCLKmode
GCLK GEN ADCLK GEN CIFCLK GEN
GCLK (DAI)
MUX
[7:6]
ADCLKmode
ADCLK (ADC)
MUX
[7:6]
CIFCLKmode
CIFCLK (Camera I/F)
Figure 8.1 Clock Generator Block Diagram WAITGEN module is for waiting until oscillation is stabilized. It blocks internal clocks until about 218 transitions occur on XIN after reset is released. If frequency of XIN is 16MHz, the wait time is about 16.4 ms (21.85ms @12MHz). The source of the system clocks (FCLK and HCLK) can be selected among XIN (main oscillator), PLLOUT (PLL output clock) and XTIN (sub-oscillator). The other clocks that are dedicated to each Preliminary 8-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR
peripheral can be driven by one of three clock sources (XIN, PLLOUT, XTIN) or divided PLL output. Each clock generation module has two modes of clock division - normal divider mode and DCO mode that is described below. The two modes can be selected by DIVMODE register. 8.1.1 DCO Control DCLK is used as the master clock of DAI (Digital Audio Interface) block if it is in master mode. EXTCLK is used for external usage especially for CD application. UTCLK is used as the main clock of UART controller. These clocks are generated by 14bit DCO (Digital Controlled Oscillator) that can generate a stable and flexible frequency as long as its frequency is below about one tenth of the divisor clock. That is, if the frequency of DCO source clock is more than ten times of that of DCO output clock, the jitter of DCO output clock can be less than 10%. For reliable operation of DAI, the frequency of divisor clock must be higher than about 240MHz as the frequency of DCLK usually has about 10 to 22 MHz. The target frequency can be acquired by writing the phase value calculated by the following equation to each PHASE register. D_PHASE EX1_PHASE EX2_PHASE UT_PHASE = 16384 * fDCLK / fDIV = 16384 * fEX1CLK / fDIV = 16384 * fEX2CLK / fDIV = 16384 * fUTCLK / fDIV
Where, fDIV is the frequency of divisor clock that is normally frequency of PLLOUT clock. For example, when you use 44.1KHz sampling rate and want to set DCLK as 256fs, the target frequency of DCLK is 256 * 44.1k = 11.2896 MHz, and if you set PLL to 266MHz, the D_PHASE value must be set to 696 (~= 16384 * 11.2896 / 266). The other clocks have 6bit DCO, so the formula for setting frequency is different from that of 14bit DCO clocks. The main difference is that the multiplication factor is changed to 64 instead of 16384. For 6bit DCO clocks, they have poorer resolution than that of 14bit DCO clocks. So it is strongly recommended to use n power of 2 as a phase value of those clocks. In that case, the DCO simply act as a clock divider circuit. For example, if the source clock of DCO has 200MHz, the preferred frequencies for it are 100MHz, 50MHz, 25MHz, 12.5MHz, etc. For both type of DCOs, it has limited frequency that can be generated with it. The maximum frequency of DCO is a half of its divisor clock's frequency. But, by setting to 0 at its phase value, it is possible to get the same frequency as its divisor clock's frequency. Table 8.1 Example of Phase for Several Target Frequencies Target 6bit DCO 14bit DCO Description fIN 0x00 0x0000 Bypass (fOUT = fIN) fIN / 2 0x20 0x2000 Divide by 2 (fOUT = fIN / 2) fIN / 4 0x10 0x1000 Divide by 4 (fOUT = fIN / 4) fIN / 8 0x08 0x0800 Divide by 8 (fOUT = fIN / 8) fIN / 16 0x04 0x0400 Divide by 16 (fOUT = fIN / 16) fIN / 32 0x02 0x0200 Divide by 32 (fOUT = fIN / 32)
Preliminary
8-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR
8.1.2 Power Down Mode In power down mode, all the clocks including the main oscillator (XIN) can be disabled for maxmum power saving. There are three possible cases in power down mode. 1. 2. 3. All the clocks stopped 32-bit counter running with XTIN clock input. All or part of the peripherals running with XTIN clock input.
The XTIN clock can be managed to remain enabled, by setting either XTE bit of PLLmode to 1 or XTTC32 bit of PWDCTL to 0. (Refer to Figure 8.2 for control bit usages). Before power down mode is enabled, "Interrupt Enable Register" and "Wakeup Event Register" must be programmed appropriately. Any bit enabled in these registers can wakeup the system from the power down mode. If sub-oscillator (XTIN) is not used or disabled in power down mode (case 1 above), only the external interrupt pins (GPIO_A[15:12]/EXINT[3:0]) can wake up the system. In this case, the corresponding bit(s) of "Wakeup Event Register" must be enabled. Refer to Section "Interrupt Controller" for "Wakeup Event Register" description. When HCLK is stopped (case 2 above), the TCC76x interrupt controller stops immediately and does not work. Only the following events are masked by "Wakeup Event Register" and sent to the clock wakup circuitry. - 32-bit timer interrupt - external interrupt pins (GPIO_A[15:12]/EXINT[3:0]) It is recommended to disable "Interrupt Enable Register" and use "Wakeup Event Register" in all cases. Right after exit from power down mode, the XIN crystal starts oscillation and the processor waits until the input frequency is stabilized, and continues to operate at the next instruction. Note that the XTIN input has no wait logic for crystal stabilization. Thus, do not disable XTIN oscillator input when the CPU is running with XTIN. Power down mode can be entered by writing a "1" to PDN bit of CKCTRL register. 8.1.3 IDLE Mode In idle mode, the FCLK of the ARM940T is disabled and HCLK can be disabled optionally by using HD bit of SCLKmode register. Before Idle mode is enabled, "Interrupt Enable Register" and "Wakeup Event Register" must be programmed appropriately. Any bit enabled in these registers can wakeup the system from the Idle mode. As explained in previous section, the TCC76x interrupt controller does not work when HCLK is stopped. So, make sure to disable "Interrupt Enable Register" and use "Wakeup Event Register" if HCLK is to be stopped. Idle mode can be entered by writing a "1" to IDLE bit of CKCTRL register. Refer to the description of PWDCTL and HCLKSTOP register for additional power control options which can be used in idle mode.
Preliminary
8-3
TCC76x
8.2 Register Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR
Table 8.2 Clock Generator Register Map (Base Address = 0x80000400) Name Address Type Reset Description CKCTRL 0x00 R/W 0x00007FFE Clock Control Register PLLMODE 0x04 R/W 0x00002E02 PLL Control Register SCLKmode 0x08 R/W 0x00082000 System Clock Control Register DCLKmode 0x0C R/W 0x00000800 DCLK (DAI/CODEC) Control Register EACLKmode 0x10 R/W 0x00000000 ADCLK and EX2CLK Control Register EX1CLKmode 0x14 R/W 0x00000000 EX1CLK Control Register UTCLKmode 0x18 R/W 0x000001BE UTCLK (UART) Control Register UBCLKmode 0x1C R/W 0x00000000 UBCLK (USB) Control Register LCLKmode 0x20 R/W 0x00000000 LCLK (LCD) Control Register TCLKmode 0x24 R/W 0x00000000 TCLK (Timer) Control Register GCLKmode 0x28 R/W 0x00000000 GCLK (GSIO) Control Register CIFCLKmode 0x2C R/W 0x00000000 CIFCLK Control Register SW_nRST 0x3C R/W 0x0000FEFF Software Reset for each peripherals PWDCTL 0x40 R/W 0x00000000 Power Down Control DIVMODE 0x44 R/W 0x00000000 Divider Mode Enable (DCO Disable) HCLKSTOP 0x48 R/W 0x00000000 HCLK Stop Control
XTIN is selected if PW DCTL[7] (XTTC32) == 0
ZCLK
MUX
(32-bit Counter Clock) DCO/Divider selected if (SCLKmode[5:0] != 0)
XIN
!CKCTRL[25]
MUX
MUX
DIVCLK0 MUX
FCLK
XTIN
PW DCTL[17] (XTFCLK)
DCO / Divider
!CKCTRL[24]
PLLmode[18] !CKCTRL[12] & !PW DCTL[7] | (!CKCTRL[25] | PLLmode[19]) !CKCTRL[12] & (!CKCTRL[25] | PLLmode[19]) SCLKmode[5:0] (F_PHASE) DCO/Divider selected if (SCLKmode[13:8] != 0)
PLL
!CKCTRL[11] (PLL)
PLLOUT
MUX
MUX DIVCLK1
MUX
HCLK to CPU
SCLKmode[15] ? PW DCTL[17] : PW DCTL[16]
DCO / Divider
!CKCTRL[24] | SCLKmode[14]
Gated HCLK to each peripheral
SCLKmode[13:8] (H_PHASE) HCLKSTOP[14:0]
Divider
PLLDIVCLK
MUX
MUX
DCLK
PW DCTL[9:8] (DVPLL)
DCLKmode[15:14] (DIVD)
DCO / Divider
!CKCTRL[1]
DCLKmode[13:0] (D_PHASE)
* * *
Figure 8.2 Clock Generator Register Signals
Preliminary
8-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR
Clock Control Register (CKCTRL) 0x80000400 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 PDN IDLE 0 TSTCK 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 CIF ADC XTIN PLL UBH GCK TCK LCK USB UART EX1 EX2 0 DAI 0 This register controls various sources of clocks fed to each peripheral. If each control bit (Bit [14:0]) is set to 1, the corresponding clock is disabled and the peripherals using that clock are also disabled. To enable the clock, clear the control bit to 0. Bit Name Type Default Description 31:26 Reserved R 0 Reserved 25 PDN W 0 Power Down Mode Enable. When this bit is written with "1", all blocks are disabled. Do not enable this bit when the PLL is enabled and PLLOUT is selected. This bit is write-only, always read as zero. 24 IDLE W 0 Idle Mode Enable. When this bit is written with "1", only the CPU is disabled. Do not enable this bit when the PLL is enabled and PLLOUT is selected. This bit is write-only, always read as zero. 23:20 Reserved R 0 Reserved 19:16 TSTCK R/W 0 Test Clock Output Selection (GPIO_B0 with GTSEL_B0 = 1). Prior to use this field, user must set GPIO_B0 port appropriately. The GTSEL_B0 should be set to 1, and the GSEL_B0 should be set to 0. Care must be taken not to use SDRAM in this mode, because the GPIO_B0 pin is shared with SD_CKE signal.
0x0 ~ 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF Set to Low PLLOUT PLLOUT xor DIVCLK1(either PLLOUT or XIN) DIVCLK1 xor TCLK xor GCLK CIFCLK xor DCLK xor EX2CLK FCLK xor UHCLK xor EX1CLK UTCLK xor UDCLK LCLK xor ADCLK xor EX1CLK
15 14 13 12 11 10 9 8 7 6 5 4 3
Reserved R CIF R/W ADC R/W XTIN R/W PLL UBH GCK TCK LCK USB UART EX1 EX2 R/W R/W R/W R/W R/W R/W R/W R/W R/W
0 1 1 1 1 1 1 1 1 1 1 1 1
2 1 0
Reserved R DAI R/W Reserved R
1 1 0
Reserved CIF Clock Control (0 = Enable, 1 = Disable) ADC Clock Control (0 = Enable, 1 = Disable) Sub Oscillator Clock Control (0 = Enable, 1 = Disable) This bit has no effect if XTTC32 of PWDCTL is "0" (XTIN always enabled). PLL Control (0 = Enable, 1 = Disable) USB Host Clock Control (0 = Enable, 1 = Disable) GSIO Clock Control (0 = Enable, 1 = Disable) Timer Clock Control (0 = Enable, 1 = Disable) LCD Clock Control (0 = Enable, 1 = Disable) USB Device Clock Control (0 = Enable, 1 = Disable) UART Clock Control (0 = Enable, 1 = Disable) EXT1 Clock Control (0 = Enable, 1 = Disable) The EX1 clock can be monitored through GPIO_B29, GPIO_B24, GPIO_B5, GPIO_B4, GPIO_B3, and GPIO_B2 pins. (Refer to Chapter GPIO) EXT2 (I2C) Clock Control (0 = Enable, 1 = Disable) The EX2 clock can be monitored through GPIO_B28, GPIO_A9 and GPIO_A10 pins. Refer to GPIO chapter for more information. The EX2 clock is also a source clock for the I2C core module. Reserved DAI Clock Control (0 = Enable, 1 = Disable) Reserved
Preliminary
8-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR 0x80000404 21 20 19 18 17 16 LOCK XTE DIV1 S 5 4 3 2 1 0 P
PLL Control Register (PLLmode) 31 30 29 28 27 26 25 0 15 14 13 12 11 10 9 Reserved M Bit Name 31:21 Reserved 20 LOCK Type R R
24 8
23 7 0
22 6 0
19
XTE
R/W
Default Description 0 Reserved 0 PLL Lock Counter Flag indicates that the internal PLL is in lock state. This flag is generated from a counter, which runs with XIN oscillator clock input. In case of 12MHz frequency, this bit will be set at about 341s after PLL is enabled. This bit is cleared when PLL bit (Bit [11]) of CKCTRL register is set. Do not look up this flag when PLL S/M/P parameter values are changed. 0 XTIN Enable in Power Down Mode.
0 1 XTIN is disabled in power down mode XTIN is controlled by XTIN bit of CKCTRL register
18 17:16 15:14 13:8 7:6 5:0
DIV1 S Reserved M Reserved P
R/W R/W R R/W R R/W
0 0 0 0x2E 0 0x0E
This bit has no effect if XTTC32 bit of PWDCTL register is 0 (XTIN is always enabled). Divisor Clock Select 0 Use Oscillator input as DIVCLK1 and DIVCLK0 1 Use PLL output as DIVCLK1 and DIVCLK0 PLL Post-Scaler (0 S 3) Reserved PLL Main-Divider (1 P 62) Reserved PLL Pre-Divider (1 P 62)
S/M/P PLL Frequency Setting S [1:0] Post-Scaler (0 S 3) M[5:0] Main-Divider (1 P 62) P [5:0] Pre-Divider (1 P 62) The PLL output frequency can be acquired by the following equation. fPLL = fXin * 8 * (M + 2) / ((P + 2) * 2S ) Where, M, P, S can be set by PLLmode register. Note that not all the M and P parameter combinations are valid. Make sure to check the stability of the resulting frequency. The PLL has a standby mode to minimize power consumption. It is controlled by PLL bit of CKCTRL register.
Preliminary
8-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR
System Clock Control Register (SCLKmode) 0x80000408 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HS HD H_PHASE 0 F_PHASE It generates FCLK, HCLK for system operation. FCLK is dedicated for the ARM940T processor, HCLK is used as internal AHB bus clock that is fed to almost internal peripherals including ARM940T processor, memory controller, DMA controller, etc. Each clock can be generated either by DCO mode or Divider mode. The 6bit DCO (Digital Controlled Oscillator) can generate a variable frequency as long as its frequency is below about one tenth of divisor clock's frequency. For reliable operation, keep the n power of 2 relationships with divisor clock, so the DCO act like a simple clock divider. (To keep the n power of 2 relationship between fSCLK and fDIV in DCO mode, the phase value must be one of the 0, 32, 16, 8, 4, 2, 1). The target frequency can be acquired by writing the phase value calculated by the following equation to the PHASE register. For the DCO Mode (when DIVMODE[1] is "0"), PHASE = 64 * fSCLK / fDIV (PHASE must be less or equal to 32) For the Divider Mode (when DIVMODE[1] is "1"), PHASE = fDIV / fSCLK - 1
Although the DCO mode can generate flexible frequency outputs, it has irreqular clock duty and jitter which may cause unexpected timing problem especially with external bus components. Timing parameters programmd in memory control registers should have sufficient margin to compensate the irregularity of the DCO. It is strongly recommended to use Divider mode (refer to DIVMODE register) rather than DCO mode.
Bit Name 31:16 Reserved 15 HS
Type R R/W
Default Description 0x0008 Reserved 0 HCLK Clock Select
0 1 Enable XTHCLK bit of PWDCTL register. Disable XTHCLK bit of PWDCTL register. PWDCTL[16] signal, which is shown in Figure 8.1, is replaced with PWDCTL[17].
14
HD
R/W
0
HCLK Clock Disable in IDLE Mode
0 In idle mode, HCLK is enabled 1 In idle mode, HCLK is disabled By using this flag, the power of peripherals driven by HCLK especially for memory controller can save more power in idle mode. This flag must be used carefully because by setting this flag, most of the internal modules including the memory controller are stopped in idle mode. Also note that interrupt request from the internal core modules are not available if HCLK is disabled. The external interrupt pins and the 32-bit counter running with XTIN clock are valid wake up events in this case. If you want to use another interrupt source as an wakeup event, do not disable HCLK with HD bit. Instead, use HCLKSTOP register to disable each peripheral individually.
13:8
H_PHASE
R/W
0x20
HCLK Frequency Select
DIVMODE[1] 0 0 0 1 H_PHASE 0 1 ~ 0x20 > 0x20 X fHCLK (HCLK Frequency) fDIV or fFCLK (depends on HS bit) fDIV * H_PHASE / 26 Undefined. Do not use. fDIV / (H_PHASE + 1)
7:6 5:0
Reserved F_PHASE
R R/W
0 0
Reserved FCLK Frequency Select
DIVMODE[0] 0 0 0 1 F_PHASE 0 1 ~ 0x20 > 0x20 X fFCLK (FCLK Frequency) fDIV fDIV * F_PHASE / 26 Undefined. Do not use. fDIV / (F_PHASE + 1)
Preliminary
8-7
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR 0x8000040C 18 17 16 2 1 0
DCLK (DAI) Control Register (DCLKmode) 31 30 29 28 27 26 25 24 23 22 21 0 15 14 13 12 11 10 9 8 7 6 5 DIVD D_PHASE[13:0] Bit Name 31:16 Reserved 15:14 DIVD
20 4
19 3
Type Default Description R 0 Reserved R/W 0 DCLK Divisor Clock Select DIVD fDIVD (Divisor Clock Source Selected)
0 1 2 3 XIN input PLL output XTIN input PLLDIVCLK (PLL clock divider output)
13:0
D_PHASE
R/W
0x0800 DCLK Clock Frequency Select
DCLK is also controlled by DAI bit of CKCTRL register that can enable or disable DCLK. If this bit is set to high, DCLK is disabled and if it is low, DCLK is enabled. DCLK is for DAI which requires 512*fs frequency. To make DCLK of this frequency, first set the frequency of PLL (fDIV) more higher than 512*fs and set D_PHASE according to the above formulae. It is recommended to set the frequency of PLL by the n power of 2, than the duty ratio of DCLK is only dependant of that of PLL clock.
Preliminary
8-8
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR 0x80000410 20 19 18 17 16 AD_PHASE[5:0] 4 3 2 1 0
EACLK (External/ADC) Control Register (EACLKmode) 31 30 29 28 27 26 25 24 23 22 21 0 DIVAD 15 14 13 12 11 10 9 8 7 6 5 DIVX2 EX2_PHASE[13:0] Bit Name 31:24 Reserved 23:22 DIVAD
Type Default Description R 0 Reserved R/W 0 ADCLK Divisor Clock Select DIVAD fDIVAD (Divisor Clock Source Selected)
0 1 2 3 XIN input PLL output XTIN input PLLDIVCLK (PLL clock divider output) AD_PHASE 0 1 ~ 0x2000 > 0x2000 X fADCLK (ADCLK Frequency) fDIVAD fDIVAD* AD_PHASE / 214 Undefined. Do not use. fDIVAD / (AD_PHASE + 1)
21:16 AD_PHASE
R/W
0
ADCLK Clock Frequency Select
DIVMODE[5] 0 0 0 1
15:14 DIVX2
R/W
0
EX2CLK / I2C Divisor Clock Select DIVX2 fDIVX2 (Divisor Clock Source Selected)
0 1 2 3 XIN input PLL output XTIN input PLLDIVCLK (PLL clock divider output) EX2_PHASE 0 1 ~ 0x2000 > 0x2000 X fEX2CLK (EX2CLK Frequency) fDIVX2 fDIVX2 * EX2_PHASE / 214 Undefined. Do not use. fDIVX2 / (EX2_PHASE + 1)
13:0
EX2_PHASE
R/W
0
EX2CLK / I2C Clock Frequency Select
DIVMODE[4] 0 0 0 1
ADCLK is also controlled by ADC bit of CKCTRL register that can enable or disable ADCLK. If this bit is set to high, ADCLK is disabled and if it is low, ADCLK is enabled EX2CLK is also controlled by EX2 bit of CKCTRL register that can enable or disable EX2CLK. If this bit is set to high, EX2CLK is disabled and if it is low, EX2CLK is enabled. External clock is a user-programmable clock that can be used for various purposes. By setting GPIO registers, GPIO_A10, GPIO_A9 and GPIO_B28 pins can output this clock to user application board. Care must be taken not to use too high frequency that the these pins cannot cope with this signals, or the pins show no clock signal out. EX2CLK is also a clock source for internal I2C core module. When it is used as an external clock, internal I2C core may not function dependent on the clock frequency. EX2CLK must be programmed to meet the following equation if I2C core is enabled. fEX2CLK fHCLK / 4.0
Preliminary
8-9
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR 0x80000414 18 17 16 2 1 0
EX1CLK Control Register (EX1CLKmode) 31 30 29 28 27 26 25 24 23 22 21 0 15 14 13 12 11 10 9 8 7 6 5 DIVX1 EX1_PHASE[13:0] Bit Name 31:16 Reserved 15:14 DIVX1
20 4
19 3
Type Default Description R 0 Reserved R/W 0 EX1CLK Divisor Clock Select DIVX1 fDIVX1 (Divisor Clock Source Selected)
0 1 2 3 XIN input PLL output XTIN input PLLDIVCLK (PLL clock divider output) EX1_PHASE 0 1 ~ 0x2000 > 0x2000 X fEX1CLK (EX1CLK Frequency) fDIVX1 fDIVX1 * EX1_PHASE / 214 Undefined. Do not use. fDIVX1 / (EX1_PHASE + 1)
13:0
EX1_PHASE
R/W
0
EX1CLK Clock Frequency Select
DIVMODE[6] 0 0 0 1
EX1CLK is also controlled by EX1 bit of CKCTRL register that can enable or disable EX1CLK. If this bit is set to high, EX1CLK is disabled and if it is low, EX1CLK is enabled. External clock is user-programmable clock that can be used various purposes. It is not used by internal peripherals, and by setting GPIO registers, GPIO_B29, GPIO_B24 and GPIO_B[5:2] pins can output this clock to user application board. Care must be taken not to use too high frequency that these pins cannot cope with.
UTCLK (UART) Control Register (UTCLKmode) 31 30 29 28 27 26 25 24 23 22 21 0 15 14 13 12 11 10 9 8 7 6 5 DIVUT UT_PHASE[13:0] Bit Name 31:16 Reserved 15:14 DIVUT
20 4
19 3
0x80000418 18 17 16 2 1 0
Type Default Description R 0 Reserved R/W 0 UTCLK Divisor Clock Select DIVUT fDIVUT (Divisor Clock Source Selected)
0 1 2 3 XIN input PLL output XTIN input PLLDIVCLK (PLL clock divider output) UT_PHASE 0 1 ~ 0x2000 > 0x2000 X fUTCLK (UTCLK Frequency) fDIVUT fDIVUT * UT_PHASE / 214 Undefined. Do not use. fDIVUT / (UT_PHASE + 1)
13:0
UT_PHASE
R/W
0x1BE
UTCLK Clock Frequency Select
DIVMODE[7] 0 0 0 1
UTCLK is also controlled by UART bit of CKCTRL register that can enable or disable UTCLK. If this bit is set to high, UTCLK is disabled and if it is low, UTCLK is enabled This clock is used by UART. For reliable communication with host side, this clock has the frequency of 3.6864MHz or so. The UART clock is then divided by DL register in UART block, it is not so important to maintain the duty ratio of 50%.
Preliminary
8-10
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR 0x8000041C 18 17 16 0
UBCLK (USB) Control Register (UBCLKmode) 31 30 29 28 27 26 25 24 23 22 0 15 14 13 12 11 10 9 8 7 6 0 DIVUB 0 UBCLK is used as the main clock of both USB Host and Device block. Bit Name 31:10 Reserved 9:8 DIVUB
21 5
20 4
19
3 2 1 UB_PHASE[5:0]
Type Default Description R 0 Reserved R/W 0 UBCLK Divisor Clock Select DIVUB fDIVUB (Divisor Clock Source Selected)
0 1 2 3 XIN input PLL output XTIN input PLLDIVCLK (PLL clock divider output)
7:6 5:0
Reserved UB_PHASE
R R/W
0 0
Reserved UBCLK Clock Frequency Select
DIVMODE[8] 0 0 0 1 UB_PHASE 0 1 ~ 0x20 > 0x20 X fUBCLK (UBCLK Frequency) fDIVUB fDIVUB * UB_PHASE / 26 Undefined. Do not use. fDIVUB / (UB_PHASE + 1)
UBCLK is gated separately by "UBH" bit and "USB" bit of CKCTRL register to generate UHCLK (for Host Controller) and UDCLK (for Device Controller).
LCLK (LCD) Control Register (LCLKmode) 31 30 29 28 27 26 25 24 23 22 0 15 14 13 12 11 10 9 8 7 6 0 DIVLCD 0 Bit Name 31:10 Reserved 9:8 DIVLCD
21 5
20 4
19
0x80000420 18 17 16 0
3 2 1 LCD_PHASE[5:0]
Type Default Description R 0 Reserved R/W 0 LCLK Divisor Clock Select DIVLCD fDIVLCD (Divisor Clock Source Selected)
0 1 2 3 XIN input PLL output XTIN input PLLDIVCLK (PLL clock divider output)
7:6 5:0
Reserved R LCD_PHASE R/W
0 0
Reserved LCLK Clock Frequency Select
DIVMODE[9] 0 0 0 1 LCD_PHASE 0 1 ~ 0x20 > 0x20 X fLCLK (LCLK Frequency) fDIVLCD fDIVLCD * LCD_PHASE / 26 Undefined. Do not use. fDIVLCD / (LCD_PHASE + 1)
LCLK is also controlled by LCK bit of CKCTRL register that can enable or disable LCLK. If this bit is set to high, LCLK is disabled and if it is low, LCLK is enabled.
To avoid LCD FIFO underrun, LCLK frequency must be set below HCLK frequency. fLCD < fHCLK
Preliminary
8-11
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR 0x80000424 18 17 16 0
TCLK (Timer) Control Register (TCLKmode) 31 30 29 28 27 26 25 24 23 22 0 15 14 13 12 11 10 9 8 7 6 0 DIVT 0 Bit Name 31:10 Reserved 9:8 DIVT
21 5
20 4
19
3 2 1 TC_PHASE[5:0]
Type Default Description R 0 Reserved R/W 0 TCLK Divisor Clock Select DIVT fDIVT (Divisor Clock Source Selected)
0 1 2 3 XIN input PLL output XTIN input PLLDIVCLK (PLL clock divider output)
7:6 5:0
Reserved T_PHASE
R R/W
0 0
Reserved TCLK Clock Frequency Select
DIVMODE[10] 0 0 0 1 T_PHASE 0 1 ~ 0x20 > 0x20 X fTCLK (TCLK Frequency) fDIVT 6 fDIVT * T_PHASE / 2 Undefined. Do not use. fDIVT / (T_PHASE + 1)
TCLK is also controlled by TCK bit of CKCTRL register that can enable or disable TCLK. If this bit is set to high, TCLK is disabled and if it is low, TCLK is enabled.
GCLK (GSIO) Control Register (GCLKmode) 31 30 29 28 27 26 25 24 23 22 0 15 14 13 12 11 10 9 8 7 6 0 DIVG 0 Bit Name 31:10 Reserved 9:8 DIVG
21 5
20 4
19
0x80000428 18 17 16 0
3 2 1 GC_PHASE[5:0]
Type Default Description R 0 Reserved R/W 0 GCLK Divisor Clock Select DIVG fDIVG (Divisor Clock Source Selected)
0 1 2 3 XIN input PLL output XTIN input PLLDIVCLK (PLL clock divider output)
7:6 5:0
Reserved G_PHASE
R R/W
0 0
Reserved GCLK Clock Frequency Select
DIVMODE[11] 0 0 0 1 G_PHASE 0 1 ~ 0x20 > 0x20 X fGCLK (GCLK Frequency) fDIVG fDIVG * G_PHASE / 26 Undefined. Do not use. fDIVG / (G_PHASE + 1)
GCLK is also controlled by GCK bit of CKCTRL register that can enable or disable GCLK. If this bit is set to high, GCLK is disabled and if it is low, GCLK is enabled.
Preliminary
8-12
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR 0x8000042C 18 17 16 0
CIFCLK Control Register (CIFCLKmode) 31 30 29 28 27 26 25 24 0 15 14 13 0 Bit Name 31:10 Reserved 9:8 DIVCIF 12 11 10 9 8 DIVCIF
23 7 0
22 6
21 5
20 4
19
3 2 1 CIF_PHASE[5:0]
Type Default Description R 0 Reserved R/W 0 CIFCLK Divisor Clock Select DIVCIF fDIVCIF (Divisor Clock Source Selected)
0 1 2 3 XIN input PLL output XTIN input PLLDIVCLK (PLL clock divider output)
7:6 5:0
Reserved CIF_PHASE
R R/W
0 0
Reserved CIFCLK Clock Frequency Select
DIVMODE[12] 0 0 0 1 CIF_PHASE 0 1 ~ 0x20 > 0x20 X fCIFCLK (CIFCLK Frequency) fDIVCIF 6 fDIVCIF * CIF_PHASE / 2 Undefined. Do not use. fDIVCIF / (CIF_PHASE + 1)
CIFCLK is also controlled by CIF bit of CKCTRL register that can enable or disable CIFCLK. If this bit is set to high, CIFCLK is disabled and if it is low, CIFCLK is enabled.
Software Reset Register (SW_nRST) 0x8000043C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CIF LCD DMA UBH ETC ECC FGP I2C GS UT UB GP TC IC DAI This register can be used to generate a reset signal within a certain peripheral. If one of bits in this register is set to 0, the corresponding peripheral is initialized as like as a system reset has been issued and remained in initialization state until the corresponding bit is released back to 1. Bit Name Type Default Description 14 CIF R/W 1 CIF Block Reset Control 13 LCD R/W 1 LCD Block Reset Control 12 DMA R/W 1 DMA Block Reset Control 11 UBH R/W 1 USB Host Block Reset Control 10 ETC R/W 1 Miscellaneous Block Reset Control. 9 ECC R/W 1 ECC Block Reset Control 8 FGP R/W 0 Fast GPIO Block Reset Control 7 I2C R/W 1 I2C Block Reset Control 6 GS R/W 1 GSIO Block Reset Control 5 UT R/W 1 UART/IrDA Block Reset Control 4 UB R/W 1 USB Device Block Reset Control 3 GP R/W 1 GPIO Block Reset Control 2 TC R/W 1 Timer/Counter Block Reset Control 1 IC R/W 1 Interrupt Controller Block Reset Control 0 DAI R/W 1 DAI/CDIF Block Reset Control Miscellaneous block contains ADC, Leading Zero Counter register, and other system configuration registers. Soft reset for this block is not recommended.
Preliminary
8-13
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR
Power Down Mode Control Register (PWDCTL) 0x80000440 Bit Name Type Default Description 31:18 Reserved R 0 17 XTFCLK R/W 0 Select XTIN for FCLK. If DIV1 bit of PLLmode register is "0" and this bit is set as "1", clock source for FCLK and HCLK is changed to XTIN. 16 XTHCLK R/W 0 Select XTIN for HCLK. If DIV1 bit of PLLmode register is "0" and this bit is set as "1", clock source for HCLK is changed to XTIN. The functionality of this bit is disabled when HS bit of SCLKmode register is "1". 15:10 Reserved R/W 0 9:8 DVPLL R/W 0 Clock Divisor Value for the PLL Divider described in Figure 8.1. Use the divider when the PLL output frequency is too high. DVPLL PLLDIVCLK 00 Disabled 01 PLLOUT / 2 10 PLLOUT / 3 11 PLLOUT / 4 7 XTTC32 R/W 0 Clock select for 32-bit counter. Do not change when the counter is enabled. 0: XTIN 1: XIN When this bit 0, XTIN oscillator is always enabled regardless of the other register bits which controls XTIN oscillator. 6 CPUREQ R/W 0 CPU bus request control in IDLE mode. 0: Disable the bus request signal from the CPU 1: Enable the bus request signal from the CPU 5 PAUSE R/W 0 PAUSE the arbiter in IDLE mode. 0: Enable the AHB arbiter 1: Pause the AHB arbiter 4 CTLHCKE R/W 0 HCLK Enable in Power Down Mode. For test purpose only. 3 XTINEN R/W 0 Force XTIN Oscillator Enabled. For test purpose only. 2 XTINCKE R/W 0 Force XTIN Clock Enabled. For test purpose only. 1 XINEN R/W 0 Force XIN Oscillator Enabled. For test purpose only. 0 XINCKE R/W 0 Force XIN Clock Enabled. For test purpose only.
Note: Except for XTTC32 bit, all the default values were selected to keep the TCC72x compatibility.
Preliminary
8-14
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR
Divider Mode Enable Register (DIVMODE) 0x80000444 Bit Name Type Default Description 31:13 Reserved R 0 12 DVMCIF R/W 0 Divider Mode Enable for CIF Clock (CIFCLK) 11 DVMGSIO R/W 0 Divider Mode Enable for GSIO Clock (GCLK) 10 DVMTC R/W 0 Divider Mode Enable for Timer/Counter Clock (TCLK) 9 DVMLCD R/W 0 Divider Mode Enable for LCD Clock (LCLK) 8 DVMUSB R/W 0 Divider Mode Enable for USB Clock (UHCLK, UDCLK) 7 DVMUART R/W 0 Divider Mode Enable for UART/IrDA Clock (UTCLK) 6 DVMEXT R/W 0 Divider Mode Enable for External Clock (EX1CLK) 5 DVMADC R/W 0 Divider Mode Enable for ADC Clock (ADCLK) 4 DVMI2C R/W 0 Divider Mode Enable for I2C Clock (EX2CLK) 3 DVMDAI R/W 0 Divider Mode Enable for DAI Clock (DCLK) 2 Reserved R/W 0 1 DVMAHB R/W 0 Divider Mode Enable for AHB Clock (HCLK) 0 DVMCPU R/W 0 Divider Mode Enable for CPU Clock (FCLK) Each bit selects clock division mode of corresponding clock generator. When set to high, DCO mode is disabled and the clock generator works as a simple divider. The PHASE field of the following registers are used as divisor values; SCLKmode DCLKmode EACLKmode EX1CLKmode UTCLKmode UBCLKmode LCLKmode TCLKmode GCLKmode CIFCLKmode The clock generator output frequency is determined by the following equation. fOUT = fMUX / (PHASE + 1) Where, fMUX is the frequency of multiplexer output (refer to Figure 8.1). As described above, PHASE field has different meaning in the two modes. DIVMODE register should be programmed only when the corresponding clock is disabled or PHASE value is "0" (fOUT = fMUX). Otherwise, unexpected clock frequency is fed to core modules until correct PHASE value is written.
Preliminary
8-15
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CLOCK GENERATOR
HCLK Bit 31:15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Stop Control Register (HCLKSTOP) 0x80000448 Name Type Default Description Reserved R 0 HSTOPCIF R/W 0 HCLK Stop Control for CIF Block HSTOPLCD R/W 0 HCLK Stop Control for LCD Block HSTOPDMA R/W 0 HCLK Stop Control for DMA Block HSTOPUBH R/W 0 HCLK Stop Control for USB Host Block HSTOPETC R/W 0 HCLK Stop Control for Miscellaneous Block. HSTOPECC R/W 0 HCLK Stop Control for ECC Block Reserved R/W 0 HSTOPI2C R/W 0 HCLK Stop Control for I2C Block HSTOPGSIO R/W 0 HCLK Stop Control for GSIO Block HSTOPUART R/W 0 HCLK Stop Control for UART/IrDA Block HSTOPUSBD R/W 0 HCLK Stop Control for USB Device Block HSTOPGPIO R/W 0 HCLK Stop Control for GPIO Block HSTOPTC R/W 0 HCLK Stop Control for Timer/Counter Block HSTOPIC R/W 0 HCLK Stop Control for Interrupt Controller Block HSTOPDAI R/W 0 HCLK Stop Control for DAI/CDIF Block
This register controls HCLK (AMBA System Bus Clock) to each block individually. Writing a non-zero value to this register will stop the corresponding HCLK immediately. Care must be taken to avoid system hang-up when this register is programmed.
Preliminary
8-16
TCC76x
9 USB CONTROLLER 9.1 Overview
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER
The TCC76x supports a fully compliant to USB 1.1 specification, full-speed (12 Mbps) functions and suspend/resume signaling. The USB function controller has an endpoint EP0 for control and two in/output endpoints EP1/EP2 for bulk data transaction. The endpoint EP0 has a single 64 byte FIFO; Max packet size is 64 bytes. And the endpoint EP1 and EP2 have a single 128 byte FIFO, respectively. Max packet size of EP1 and EP2 is 64 bytes. There are 4 types of internal registers; IN_CSR OUT_CSR IN_MAXP OUT WRITE COUNT IN Control Status Register OUT Control Status Register IN Maximum Packet size Register OUT Write Count Register
Interrupt (Status) and Interrupt Enable registers are broken down into 2 banks: Endpoint Interrupts, USB Interrupts. The MAXP, ENDPOINT INTERRUPT and ENDPOINT INTERRUPT ENABLE registers are used regardless of the direction of the endpoint. The associated CSR registers correspond to the direction of endpoint. The TCC76x supports also 1 port of USB host interface that has the following features. OHCI Rev. 1.0 compliant USB Rev. 1.1 compatible 1 down stream port
Preliminary
9-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER
9.2 Register Description for USB Device Controller
Table 9.1 USB Register Map (Base Address = 0x80000500) Address Type Reset Description NON INDEXED REGISTERS UBFADR UBPWR UBEIR UBIR UBEIEN UBIEN UBFRM1 UBFRM2 UBIDX MAXP INCSR1 INCSR2 OCSR1 OCSR2 OFIFO1 OFIFO2 EP0FIFO EP1FIFO EP2FIFO DMACON DMAEP1 DMAEP2 0x00 0x04 0x08 0x18 0x1C 0x2C 0x30 0x34 0x38 0x40 0x44 0x48 0x50 0x54 0x58 0x5C 0x80 0x84 0x88 0xC0 0xC4 0xC8 R/W R/W R/W R/W R/W R/W R R W R/W R/W R/W R R/W R R R/W R/W R/W R/W R/W R/W 0x00 0x00 0x00 0x00 0x07 0x04 0x00 0x00 0x00 0x01 0x00 0x20 0x00 0x00 0x00 0x00 Unknown Unknown Unknown 0x00 Unknown Unknown Function Address Register Power Management Register Endpoint Interrupt Flag Register USB Interrupt Flag Register Endpoint Interrupt Enable Register Interrupt Enable Register Frame Number 1 Register Frame Number 2 Register Index Register IN Max Packet Register IN CSR1 Register (EP0 CSR Register) IN CSR2 Register OUT CSR1 Register OUT CSR2 Register OUT FIFO Write Count 1 Register OUT FIFO Write Count 2 Register EP0 FIFO Register EP1 FIFO Register EP2 FIFO Register DMA Control Register EP1 FIFO Access Register for DMA EP2 FIFO Access Register for DMA
Name
COMMON INDEXED REGISTER IN INDEXED REGISTERS
OUT INDEXED REGISTERS
FIFO REGISTERS
DMA REGISTERS
Preliminary
9-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER 0X80000500 2 1 0
Function Address Register (UBFADR) 15 14 13 12 11 10 9 8 Reserved
7 UP
6
5
4
3 FADR
UP [7] Function Address Update UP = 0 Function address doesn't be updated UP = 1 Function address can be updated with FADR * The MCU sets this bit whenever it updates the FADR field. This bit is write only register. FADR
[6:0]
Function Address Function address
n
This register maintains the USB Device Address assigned by the host. The control program should write the value received through a SET_ADDRESS descriptor from host to this register. The address is used for the next token. The UP bit field should be set whenever the FADR field is written. The FADR field is used after the Status phase of a Control transfer, which is signaled by the clearing of the DEND bit in the CSR registers. Power Management Register (UBPWR) 15 14 13 12 11 10 9 8 7 Reserved ISOUP ISOUP 1
[7]
6
5 4 Reserved
0x80000504 3 2 1 0 URST RSM SP ENSP
Type R/W
ISO Update Valid in ISO Mode only. If set, IRDY(IN Packet Ready) is set after a SOF token is received. If an IN token is received before a SOF token, then a zero length data packet will be sent to the host. USB Reset Indicates reset signaling is received from the host. Resume Signal Generate a resume signaling (DP is low, DN is high). Stop generating a resume signaling. Suspend Mode Indicates that the USB enters suspend mode Enable Suspend Mode Disable Suspend Mode Enable Suspend Mode
URST 1 RSM 1 0
[3]
Type R Type R/W Type R Type R/W
[2]
SP [1] 1 ENSP 0 1
[0]
This register is used for suspend, resume signaling. If ENSP filed is zero, the device will not enter suspend mode. If ENSP is 1 and there are no signals during 3ms, the USB enters suspend mode and the SP bit field is set to 1. It is cleared if USB receives resume or reset signal from host. The USB can also generate a resume signaling by setting RSM bit to 1.
Preliminary
9-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER 0x80000508 2 1 0 EP2 EP1 EP0
Endpoint Interrupt Flag Register (UBEIR) 15 14 13 12 11 10 9 8 Reserved EP2 1 EP1 1 EP0 1
[2]
7
6
5
4
3
Type R W Type R W Type R W
EP2 Interrupt Flag Indicates that the USB EP2 interrupt has been generated Clear the EP2 interrupt flag. EP1 Interrupt Flag Indicates that the USB EP1 interrupt has been generated Clear the EP1 interrupt flag. EP0 Interrupt Flag Indicates that the USB EP0 interrupt has been generated Clear the EP0 interrupt flag. 0x80000518 2 1 0 RST RSM SP
[1]
[0]
USB Interrupt Flag Register (UBIR) 15 14 13 12 11 10 9 8 Reserved RST 1
[2]
7
6
5
4
3
Type R W
Reset Interrupt Flag Indicates that the USB has received reset signaling (DP, DN is low during more than 10ms) Clear the Reset interrupt flag. Resume Interrupt Flag Indicates that the USB has received resume signaling (DP is low, DN is high during 10ms ~ 15ms) in suspend mode Clear the Resume interrupt flag. Suspend Interrupt Flag Indicates that the USB has received suspend signalizing Suspend signal is implicit signal that is generated if there is no activity for 3ms. Clear the Suspend interrupt flag.
RSM 1
[1]
Type R W
SP
[0]
Type R W
1
The suspend interrupt is generated when the USB receives suspend signaling. The SP bit field of the UBIR is set whenever there is no activity for 3ms on the bus. This interrupt is disabled in default. The resume interrupt is generated by a USB when it receives resume signaling in suspend mode. The USB reset interrupt is generated when USB controller receives the reset signaling from the host. The USB controller has two interrupt registers: UBEIR UBIR Endpoint interrupt register USB interrupt register
Preliminary
9-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER
These registers act as status registers when interrupt is generated. Once interrupt generated, it is needed to read all the interrupt registers and write back to all the registers to clear the interrupt. The endpoint interrupt register UBEIR has three bit fields that correspond to the respective endpoints. The EP0 interrupt is generated under the following conditions: * * * * * OUT Packet is ready. ORDY field is set in the of EP0 CSR register. IN Packet is ready. IRDY field is set in the of EP0 CSR register. STST (STALL Handshake Issued) flag is set. CEND (Control Transfer End) flag is set. DEND (Data Transfer End) is cleared (Indicates End of control transfer).
The EP1/E2 interrupt is generated under the following conditions: For IN endpoints * IRDY field is cleared in its CSR register. * FIFO is flushed * STST (STALL Handshake Issued) flag is set * * * For OUT endpoints ORDY field is set in its CSR register. STST (STALL Handshake Issued) flag is set
For ISO IN endpoints: UNDER_RUN bit is set IRDY field is cleared in its CSR register. FIFO is flushed For ISO OUT endpoints: ORDY field is set in its CSR register OVER RUN bit is set.
Preliminary
9-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER 0x8000051C 2 1 0 EP2 EP1 EP0
Endpoint Interrupt Enable Register (UBEIEN) 15 14 13 12 11 10 9 8 7 Reserved EP2 0 1 EP1 0 1 EP0 0 1
[0] [1] [2]
6
5
4
3
Type R/W
EP2 Interrupt Control Disable EP2 interrupt Enable EP2 interrupt EP1 Interrupt Control Disable EP1 interrupt Enable EP1 interrupt EP0 Interrupt Control Disable EP0 interrupt Enable EP0 interrupt 0x8000052C 2 1 0 RST 0 SP
Type R/W
Type R/W
USB Interrupt Enable Register (UBIEN) 15 14 13 12 11 10 9 8 Reserved RST [2] 1 0 Type R/W
7
6
5
4
3
Reset Interrupt Control Enable Reset interrupt. Disable Reset interrupt
SP [0] Type Suspend Interrupt Control 1 Enable Suspend interrupt R/W 0 Disable Suspend interrupt. *) Once suspend interrupt is generated, this interrupt must be disabled not to generate it continuously. Enable suspend interrupt right after the reset or resume interrupt is detected, and disable suspend interrupt right after that interrupt is detected.
Preliminary
9-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER 0x80000530 2 1 0
Frame Number 1 Register (UBFRM1) 15 14 13 12 11 10 9 8 Reserved Frame Number 2 Register (UBFRM2) 15 14 13 12 11 10 9 8 Reserved
7
6
5
4 3 FRM1
7
6
5
4 3 FRM2
0x80000534 2 1 0
There are two registers, UBFRM1 and UBFRM2, which inform the frame number received from the host. The UBFRM1 denotes the lower byte of frame number. The UBFRM2 denotes the higher byte of frame number. Frame number = FRM2 * 256 + FRM1
USB Index Register (UBIDX) 15 14 13 12 11 10 Reserved
9
8
7
6
5
4 IDX
3
0x80000538 2 1 0
This Index register is used to indicate the endpoint number while accessing the indexed registers: MAXP, INCSR1, INCSR2, OCSR1, OCSR2, OFIFO1, OFIFO2. Among the following registers, those denoted by suffix letter of `n' are index register. Index register means that its address is shared by each end point blocks. So if you want to access the indexed registers of EP0, write 0 to the index register ahead, and for EP1 write 1 to the index register, and so on. Max Packet Register (MAXPn) 15 14 13 12 11 10 9 Reserved MAXP [4:0] 00000 00001 00010 00100 01000 10000 Type 0x80000540 2 1 0 MAXP
8
7
6
5
4
3
R/W
Max Packet Number MAXP == 8 bytes (Default) MAXP == 8 bytes MAXP == 16 bytes MAXP == 32 bytes MAXP == 64 bytes MAXP == 128 bytes (EP1, EP2 ISO mode only)
Preliminary
9-7
TCC76x
EP0 CSR Register (EP0CSR) 15 14 13 12 11 10 Reserved
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER 0x80000544 2 1 0
STST IRDY ORDY
9
8
7
CLSE
6
CLOR
5
ISST
4
3
CEND DEND
This register has the control and status bits for EP0 endpoint. Since a control transaction involves both IN and OUT tokens, there is only one CSR register, mapped to INCSR1 register. EP0CSR register can access by writing "0" to UBIDX register. CLSE [7] 1 CLOR 1 ISST 1 0 CEND
[4] [6]
Type W Type W Type R/W
Clear Setup End Bit The CEND flag is cleared when writing a 1 to this bit. Clear Output Packet Ready Bit The ORDY flag is cleared when writing a 1 to this bit. Issue STALL Handshake If USB decodes an invalid token, the CPU writes a 1 to this and CLOR bit concurrently. The USB issues a STALL handshake to the current control transfer. End the STALL condition by writing a 0 to this bit.
[5]
Type
1
R
Control Transfer End Indicates that the control transfer ends before DEND bit is set. It is cleared by writing a 1 to CLSE bit. When this is set, an interrupt occurs and the USB flushes FIFO and invalidates all access to FIFO.
*) When CEND bit is set, the ORDY bit also may be set. This happens when the current transfer has ended, and a new control transfer is received before the MCU can service the interrupt. In such a case, the CPU should first clear the CEND flag, and then start servicing the new control transfer.
DEND
[3]
Type
1
R/W
Data End CPU write a 1 to this bit: - after loading the last packet of data into the FIFO, at the same time IRDY flag is set. - while it clears ORDY after unloading the last packet of data. - for a zero length data phase, when it clears ORDY flag and sets IRDY flag. In the case of a control transfer where there is no data phase, the CPU (after unloading the setup token) sets DEND at the same time it clears ORDY for the setup token. STALL Handshake Issued Indicates that a control transaction is ended due to a protocol violation. An interrupt is generated when this bit is set. Clear STST flag by writing 0. IN Packet Ready After writing a packet of data into EP0 FIFO, set this bit to 1. 9-8
STST 1 0 IRDY 1
[2]
Type R W
[1]
Type W
Preliminary
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER
0
R
Indicates that the packet has been successfully sent to host. An interrupt is generated when the this bit is cleared, so the CPU can load the next packet. For a zero length data phase, the CPU must set IRDY and DEND at the same time. OUT Packet Ready Indicates that a valid token is written to the FIFO. An interrupt is generated after this flag is set. The CPU can clear this by writing a 1 to CLOR bit.
ORDY [0] 1
Type R
IN CSR1 Register (INCSR1n) 0x80000544 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTGL STST ISST FLFF UNDER FNE IRDY Reserved This register maintains the status bits for IN type endpoints in EP1 or EP2. CTGL 1 STST 1 0 ISST 1 0 FLFF
[4] [6]
Type W Type R W Type R/W
Clear Data Toggle Bit The data toggle bit is cleared STALL Handshake Issued to an IN token Indicates that the STALL handshake is issued to an IN token, due to the CPU setting ISST bit. When the USB issues a STALL handshake, IRDY flag is cleared. Clear STST flag by writing 0. Issue STALL Handshake Issue a STALL Handshake to the USB. End the STALL condition. Issue FIFO Flush IN FIFO is flushed. This bit is cleared by the USB when the FIFO is flushed. The interrupt is generated when this happens. If a token is in progress, the USB waits until the transmission is complete before the FIFO is flushed. If two packets are loaded into the FIFO, only the top-most packet (one that was intended to be sent to the host) is flushed, and the corresponding IRDY bit for that packet is cleared. The USB clears this bit after flushing FIFO. Under Run Valid for Iso mode only. This bit is set when an IN token is received and the IRDY bit is not set. A zero length data packet is sent and the next packet that is loaded into the FIFO is flushed. This bit is cleared by writing 0.
[5]
[3]
Type
1
W
0 UNDER
[2]
R Type R/W
1
Preliminary
9-9
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER
FNE [1] 0 1 IRDY 1 0
[0]
Type R Type W R
IN FIFO Not Empty Indicates that no packet of data is in IN-FIFO. Indicates that at least one packet of data is in IN-FIFO. IN Packet Ready After writing a packet of data into the IN-FIFO, set this bit to 1. Indicates that the packet has been successfully sent to host. An interrupt is generated when the USB clears this bit to zero, so the CPU can load the next packet. While this bit is set, the CPU will not be able to write to the FIFO. If the ISST flag is set, IRDY flag cannot be set to 1.
*) FNE == 0 && IRDY == 0 : Indicates that there is no packet in the FIFO.
FNE == 1 && IRDY == 0 : Indicates that there is 1 packet in the FIFO. FNE == 1 && IRDY == 1 : Indicates that there are 2 packets in the FIFO.
IN CSR2 Register (INCSR2n) 15 14 13 12 11 10
Reserved
9
8
7
ASET
6
ISO
5
MDIN
4
DMA
3
0x80000548 2 1 0
Reserved
This register is used to configure IN type endpoints. ASET 0 1
[7]
Type R/W
Auto Set User set IRDY flag manually. (Default) Whenever the CPU writes MAXP data, IRDY will automatically be set by USB. If it writes less data than MAXP, it must set IRDY manually.
ISO [6] 0 1 MDIN 0 1 DMA 0 1
[5]
ISO/BULK Mode Select Configures endpoint mode as BULK. (Default) Configures endpoint mode as ISO. IN/OUT Select Configures endpoint direction as OUT type. Configures endpoint direction as IN type. (Default) DMA Enable DMA Disable. (Default) DMA Enable.
[4]
Preliminary
9-10
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER 0x80000550 2 1 0
FFL ORDY
OUT CSR1 Register (OCSR1n) 15 14 13 12 11 10 9 8 7 6 5 4 CTGL STST ISST FLFF Reserved This register maintains the status information of endpoints. CTGL 1 STST 1 0 ISST 1 0 FLFF 1 0 DERR 1
[3] [5] [7]
3
DERR OVER
Type W Type R W Type R/W
Data Toggle Bit The data toggle sequence bit is reset to DATA0. STALL Handshake Issued Indicates that the OUT token is ended with a STALL handshake. USB issues a stall handshake to the host if host sends more than MAXP data for the OUT token. Clear STST flag by writing 0. Issue STALL Handshake Issue a STALL Handshake to the USB. End the STALL condition. Issue FIFO Flush OUT FIFO is flushed. This bit can be set only when the ORDY flag is set. Stop flushing FIFO. Data Error Valid only in ISO mode. This bit should be sampled with ORDY (Bit[0]). "1" indicates the data packet due to be unloaded by the CPU has an error (either bit stuffing or CRC). If two packets are loaded into the FIFO, and the second packet has an error, then this bit gets set only after the first packet is unloaded. This bit is automatically cleared when ORDY gets cleared. OUT FIFO Over Run Valid only in ISO mode. This bit is set if the core is not able to load an OUT ISO token into the FIFO. Cleared by writing 0. OUT FIFO Full Indicates that no more packets can be accepted OUT Packet Ready Indicates the USB has loaded a packet of data into the FIFO. Clears ORDY flag by writing 0. Once the CPU reads the FIFO for the entire packet, this bit should be cleared. (refer ACLR bit of OCSR2n register)
[6]
[4]
Type R/W
Type R
OVER 1
[2]
Type R
FFL [1] 1 ORDY [0] 1 0
Type R Type R W
*) FFL == 0 && ORDY == 0 : Indicates that there is no packet in the FIFO.
FFL == 0 && ORDY == 1 : Indicates that there is 1 packet in the FIFO. FFL == 1 && ORDY == 1 : Indicates that there are 2 packets in the FIFO.
Preliminary
9-11
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER 0x80000554 2 1 0
OUT CSR2 Register (OCSR2n) 15 14 13 12 11 10 9 8 7 6 5 4 ACLR ISO Reserved This register maintains the configuration of endpoints. ACLR 1 R/W 0
[7]
3
Reserved
Type
Auto Clear Enable Auto Clear. Whenever the CPU reads data from the OUT FIFO, ORDY will automatically be cleared by the USB. Disable Auto Clear. (Default) Once the CPU reads the FIFO for the entire packet, ORDY should be cleared manually. ISO/BULK Mode Select Configures endpoint mode as BULK. (Default) Configures endpoint mode as ISO.
ISO [6] 0 1
Type R/W R/W
OUT FIFO Write Count 1 Register (OFIFO1n) 15 14 13 12 11 10 9 8 7 Reserved OUT FIFO Write Count 2 Register (OFIFO2n) 15 14 13 12 11 10 9 8 7 Reserved
6
5
4
3
0x80000558 2 1 0
OFIFO1n
6
5
4
3
0x8000055C 2 1 0
OFIFO2n
There are two registers, OFIFO1n and OFIFO2n, which maintain the write count. OFIFO1n maintains the lower bytes, while OFIFO2n maintains the higher byte. Write count = OFIFO2n * 256 + OFIFO1n When ORDY bit of OCSR1n is set for OUT endpoints, these registers maintain the number of bytes in the packet due to be read by the CPU. EP0 FIFO Register (EP0FIFO) 15 14 13 12 11 10 Reserved EP1 FIFO Register (EP1FIFO) 15 14 13 12 11 10 Reserved EP2 FIFO Register (EP2FIFO) 15 14 13 12 11 10 Reserved 0x80000580 2 1 0 0x80000584 2 1 0 0x80000588 2 1 0
9
8
7
6
5
4
FIFO
3
9
8
7
6
5
4
FIFO
3
9
8
7
6
5
4
FIFO
3
Preliminary
9-12
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER
USB DMA Control Register (DMACON) 15 14 13 12 11 10 9 8 Reserved Bit 6:5 2:1 Name EOT RUN Type R/W R/W Reset 00 00
7
6
EOT
5
4
3
0x800005C0 2 1 0
RUN CKSEL
Reserved
0
CKSEL
R/W
0
Description Force EOT. For test purpose only. Do not write in normal operation. Start DMA Command for EP1 and EP0 respectively. DREQ/DACK signaling between the USB core and the central AHB DMA controller is enabled only when one/all of these bits are set. Once set, these bits are kept asserted until cleared by corresponding EOT(End of Transfer) signal from the central AHB DMA controller. Writing a "0" has no effect on these bits. These bits are forced to "0" when the corresponding "DMA" bit of IN CSR2 Register is disabled. Clock Select for System Bus interface. By default (0), divided HCLK clock is used for the system bus interface logic of USB core. When this bit is set as "1", the clock divider is bypassed and HCLK is directly used. Do not enable this bit if HCLK frequency is above 60MHz. 0x800005C4 2 1 0
USB DMA EP1 FIFO Register (DMAEP1) 15 14 13 12 11 10 9 8 Reserved USB DMA EP2 FIFO Register (DMAEP2) 15 14 13 12 11 10 9 8 Reserved *) Do not access FIFO registers during DMA operation.
7
6
5
4
3
EP1 FIFO Data Port for DMA Controller
7
6
5
4
3
0x800005C8 2 1 0
EP2 FIFO Data Port for DMA Controller
9.3 USB Device DMA Operation
DMA operations can be started by setting the "DMA" bit (Bit[4]) of IN CSR2 Register and "RUN" bits (Bit[2:1]) of "USB DMA Control Register" described above. Before enable these bits, the USB core and the central AHB DMA controller must be programmed correctly. Be careful about the endpoint directions programmed in the USB core and Source/Destination addresses programmed in central AHB DMA controller. Source or Destination address must be one of DMAEP1(0x800005C4) and DMAEP2(0x800005C8). Do not use EP1FIFO and EP2FIFO register address. 9.3.1 OUT Endpoint DMA Operation After the USB core receives OUT data ( maximum packet size) from HOST, the endpoint which took the data will generate DREQ strobe to AHB DMA Controller as far as the FIFO isn't empty. Consequently, the number of DREQs will be equal to the number of data bytes from Host. The DMA controller can read data from the FIFO in the specific endpoint by issuing the DACK input to the core. Whenever one packet is transferred successfully from HOST to USB, the process described above shall be performed for the OUT endpoint DMA operation. This operation is repeated until EOT signal is asserted from the DMA Controller. 9.3.2 IN Endpoint DMA Operation As long as the FIFO isn't full, DREQ signal is asserted to the DMA Controller. Then, DMA controller may write one packet of data ( maximum packet size) or multiple packets of data to a specific IN endpoint FIFO with DACK until EOT is asserted.
Preliminary
9-13
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER
9.4 Register Description for USB Host Controller
The USB host controller complies with OHCI Rev 1.0. Refer to the specification of OHCI (Open Host Controller Interface) Rev 1.0 for more detailed information. The following figure illustrates a block diagram of USB host controller.
RCF0_RegData(32)
APP_SADR(8) APP_SDATA(32)
HCI Slave Block OHCI Registers
OHCI Root Hub Registers ROOT Hub & Host SIE X V R
USB
CONTROL
USB State Control
CONTROL
CONTROL
AHB to HCI wrapper
HCI_DATA(32) CONTROL
TxEnl TxDpls
PORT S/M
CONTROL
AHB Bus
HCI Bus
ED/ TD_DATA(32) APP_MDATA(32) HCM_ADR/ DATA(32) CONTROL ED/ TD_STATUS(32)
LIST Processor Block ED & TD Registers
STATUS
CONTROL
TxDmns
CONTROL
HSIE S/M
RcvData RcvDpls RcvDmns
ROOT Hub & Host SIE
HCI Master Block
HC_DATA(8) DF_DATA(8)
64x8 FIFO Control
FIFO_DATA(8) HCF_DATA(8) ADDR(6)
RH_DATA(8) DF_DATA(8)
DPLL
PORT S/M
EXT FIFO STATUS
64x8 FIFO
Figure 9.1 USB Host Controller Block Diagram
Preliminary
9-14
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER
The following table describes the address mapping of OHCI Rev1.0 registers. Table 9.2 USB Host Register Map (Base Address = 0x80000D00) Name Address Type Reset Description HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcHCCA HcPeriodCurrentED HcControlHeadED HcControlCurrentED HcBulkHeadED HcBulkCurrentED HcDoneHead HcRmInterval HcFmRemaining HcFmNumber HcPeriodStart HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus1 HcRhPortStatus2 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 R R/W R R R/W W R/W R R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00000010 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00002EDF 0x00000000 0x00000000 0x00000000 0x00000628 0x02001202 0x00000000 0x00000000 0x00000100 0x00000100
Control and status registers
Memory pointer registers
Frame counter registers
Root hub registers
Preliminary
9-15
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB CONTROLLER
Preliminary
9-16
TCC76x
10 UART/IrDA 10.1 Overview
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 UART/IRDA
The TCC76x has 1 simple UART module that can be used in programming the system software or IrDA interfacing. The block diagram of UART is in the following figure.
LSR
CR
APB
Receiver FIFO
Receiver Shift
RZ code Demod
RXD
DL Transmit FIFO Transmit Shift RZ code Modulator TXD
IR
Interrupt Generator
IREQ
IrDACFG2 IrDACFG1
Figure 10.1 UART Block Diagram This UART is simplified version of UART16550, it provides only a simple interface (TXD, RXD) between host system and TCC76x system. In the UART, there are two FIFO blocks each for transmission and reception link. Transmission FIFO has 4 bytes depth, receiving FIFO has 8 bytes depth. UART can also be used as IrDA interfacing. There is a signal transformer between IrDA signal and UART signal. The basic timing diagram of UART and IrDA data transmission is illustrated in Figure 10.2.
Preliminary
10-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 UART/IRDA
STOP = 1 bit, Parity = Even, Data = 8 bit of 0x55 Bit CLK TX Data Start Data (LSB first) Parity Stop
RZ Modulation of Data used in IrDA Transmission with PW = 3 Bit CLK TX Data TXIrDA PW
Figure 10.2 Timing Diagram of UART Transmission
10.2 Register Description
Table 10.1 UART/IrDA Register Map (Base Address = 0x80000600) Name Address Type Reset Description UTRXD UTTXD UTDL UTIR UTCR UTLSR IrDACFG1 IrDACFG2 0x00 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 R W W R/W R/W R R/W R/W Unknown Unknown 0x0000 0x000 0x000 0x0101 0x0003 0x4da1 Receiver Buffer Register Transmitter Holding Register Divisor Latch Register Interrupt Register UART Control Register Status Register IrDA Configuration Register 1 IrDA Configuration Register 2
Preliminary
10-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 UART/IRDA 0x80000600 18 17 16 0
Receiver Buffer Register (UTRXD) 31 30 29 28 27 26 25 15 14 13 12 0 11 10 9
24 0 8
23 7
22 6
21
20
19
5 4 3 2 1 Received Data (when reading)
Whenever FRX flag of IR register is set, or RA flag of LSR register is set, reading of this register gets the 1 byte of received data. Transmitter Holding Register (UTTXD) 31 30 29 28 27 26 25 24 0 15 14 13 12 0 11 10 9 8 7 6 5 4 3 2 1 Transmitting Data (when writing) 0 0x80000600 18 17 16
23
22
21
20
19
When the transmission FIFO is not full, writing of this register fills that data to transmission FIFO. Checking TF flag of LSR register can monitor the status of a transmission FIFO. Divisor Latch Register (UTDL) 31 30 29 28 27 26 15 14 13 12 11 10 0x80000604 18 17 16 2 1 0
25 9
24 0
23
22
21 5
20 4
19 3
8 7 6 Divisor Latch Value
This is for generation of the desired baud rate clock. This register is set to 0 at reset, UART is disabled until this register is set by non-zero value. The value can be calculated as follows. UTDL = fUART / (16 * desired baud rate)
The UART clock is generated by clock generator block. It is recommended that the frequency of UART clock is set to 3.6864MHz, so the desired baud rate can be acquired by writing a value to UTDL register as follows. UTDL = 230400 / (desired baud rate)
Preliminary
10-3
TCC76x
Interrupt Register (UTIR) 31 30 29 28 27 26 15 14 13 0 12 11 10
ERS
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 UART/IRDA 0x80000608 18 17 16 2
QRS
25 9
ETX
24 0 8
ERX
23 7
0
22 6
FRS
21 5
FTX
20 4
FRX
19 3
0
1
QTX
0
QRX
ERS [10] 0 1 ETX [9] 0 1 ERX 0 1
[8]
Type R/W R/W Type R/W R/W Type R/W R/W Type R R Type R R
Interrupt Control Receiver Line Status interrupt is disabled Receiver Line Status interrupt is enabled Interrupt Control Transmitter Holding Register Empty interrupt is disabled Transmitter Holding Register Empty interrupt is enabled Interrupt Control Receiver Data Available interrupt is disabled Receiver Data Available interrupt is enabled Receiver Line Status Flag Indicate that Receiver Line Status has not changed Indicate that Receiver Line Status has changed Transmitter Holding Register Empty Flag Interrupt has not generated Interrupt has generated, but not cleared
FRS [6] 0 1 FTX [5] 0 1
FRX [4] Type Receiver Data Available Flag 0 R Interrupt has not generated 1 R Interrupt has generated, but not cleared FRS, FTX, FRX is set or cleared regardless of each enable bit (ERS, ETX, ERX) settings. It can be used to follow polling method instead of interrupt method. QRS 0 1 QTX 0 1 QRX 0
[1] [2]
Type R R Type R R Type R
Interrupt Flag Indicate that Receiver Line Status interrupt has not generated Indicate that Receiver Line Status interrupt has generated Interrupt Flag Transmitter Holding Register Empty interrupt has not generated Transmitter Holding Register Empty interrupt has generated
Interrupt Flag Indicate that Receiver Data Available interrupt has not generated 1 R Indicate that Receiver Data Available interrupt has generated QRS, QTX, QRX is only set when each enable bit is set to 1. This flags is used to distinguish which interrupt has generated the UART flag of IREQ and MREQ register in interrupt controller.
[0]
Preliminary
10-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 UART/IRDA 0x8000060C 18 17 16 2 PR 1 ST 0 0
UART/IrDA Control Register (UTCR) 31 30 29 28 27 26 25 24 0 15 14 13 0 NO 0 R/W 1 BK [8] 0 1 TF [7] 1 RF [6] 1 FIFO n
[5:4] [9]
23 7 TF
22 6 RF
21 5
20
19 3
12
11
10
9 NO Type
8 BK
4 FIFO
Start Bit Width Check Check if the pulse width of start bit is more than 0.5 bit duration of baud rate Don't check the pulse width of start bit (test or boot mode only) Break Control Bit Normal operation Bit `0' is transmitted regardless of THR Reset Transmitter FIFO The transmitter FIFO is cleared Reset Receiver FIFO The receiver FIFO is cleared RX FIFO Level Select 0 = 1byte FIFO, 1 = 2 byte FIFO 2 = 4 byte FIFO, 3 = 7 byte FIFO
Type R/W Type R/W Type R/W Type R/W
If this field is set to 1, it means that the RDA flag or interrupt is influenced when the number of received data in the RX FIFO is 2. It is recommended that this field is set to 0, so right after reception of some data, the RDA flag or interrupt can be generated. PR
[3:2]
Type R/W
0 1 2, 3 ST [1] 0 1
Parity Bit Select Even parity Odd parity Parity is disabled Stop Bit 1 Stop bit 2 Stop bit
Type R/W
Preliminary
10-5
TCC76x
Line Status Register (UTLSR) 31 30 29 28 27 26 15 14 13 12 11 10 0
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 UART/IRDA 0x80000610 18 17 16 2 FE 1 PE 0 RA
25 9
24 0 8
23 7
22 6
21 5
20 4 TE
19 3 TF
TE [4] 0 1 TF [3] 0 1
Type R Type R
Transmitter FIFO Status At least 1 byte is stored in transmitter FIFO. No data is stored in transmitter FIFO Transmitter FIFO Status At least 1 byte can be stored in transmitter FIFO. No data can be stored in transmitter FIFO
Transmitter FIFO depth is fixed to 4. FE [2] 0 1 PE [1] 0 1 RA [0] 0 1 Type R Type R Type R Framing Status Stop bit is received and correct The received data in the FIFO don't have valid stop bit Parity Status Parity bit is received and correct The received data in the FIFO don't have valid parity bit Received FIFO Status No data has been received At least 1 received data is stored in the FIFO
Preliminary
10-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 UART/IRDA 0x80000614 18 17 16 2 PW 1 0
IrDA Configuration Register 1 (IrDACFG1) 31 30 29 28 27 26 25 24 23 0 15 14 13 12 11 10 9 8 7 EN P1 POL LB 0 EN
[15]
22 6
21 5
20 4
19 3
Type R/W Type R/W Type R/W Type R/W Type R/W
0 1 P1
[14]
IrDA TX Enable IrDA TX is disabled, UART mode is used IrDA TX is enabled Transmit Pulse Type Pulse width is proportional to selected baud speed Pulse width is proportional to UART base clock speed Transmit Pulse Polarity TX `0' data is converted to level high pulse TX `0' data is converted to level low pulse Loopback Normal operation Transmitted data is fed back to RX port. IrDA RZ Pulse Width Controls pulse width of TX `0' data. If PW = 3, the high pulse has duration of 3/16 of it's a bit period or 3 * 36864001 sec.
0 1 POL [13] 0 1 LB
[12]
0 1 PW
[3:0]
PW
The IrDA shares data path with UART. So all of UART registers such as baud rate, interrupt en/disable, communication control, line status also influence to IrDA mode.
Preliminary
10-7
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 UART/IRDA 0x80000618 18 17 16 2 1 MIN1 0
IrDA Configuration Register 2 (IrDACFG2) 31 30 29 28 27 26 25 24 23 0 15 14 13 12 11 10 9 8 7 EN P1 POL 0 DEC EN
[15]
22
21
20 4
19 3
6 5 MAX1
Type R/W Type R/W
0 1 P1
[14]
IrDA RX Enable IrDA RX is disabled, UART mode is used IrDA RX is enabled Receiver Pulse Type Received pulse width is proportional to selected baud speed Received pulse width is proportional to UART base clock speed Receive Pulse Polarity The polarity of received data is not inverted The polarity of received data is inverted RX Data Decision Time The decision point for receiving data, its unit has 1/16 of baud rate. Maximum number of "1"s The maximum number of "1"s to decide the received IrDA (RZ) signal as 0. If P1 is set to 1, MAX1 has the unit of 1/1843200 sec, or if P1 is set to 0, the unit of MAX1 has 1/16 of baud rate.
0 1
POL [13] 0 1 DEC
[11:8]
Type R/W Type R/W
n MAX1
[7:4]
Type
n
R/W
MIN1
[3:0]
Type
Minimum number of "1"s The minimum number of "1"s to decide the received IrDA (RZ) signal as 0. If P1 is set to 1, MIN1 has the unit of 1/1843200 sec, or if P1 is set to 0, the unit of MIN1 has 1/16 of baud rate.
n
R/W
Preliminary
10-8
TCC76x
11 GSIO PORT 11.1 Overview
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GSIO PORT
The TCC76x has four GSIOs (General Purpose Serial Input/Output) for communication between the TCC76x and other devices that have serial interface. All the pins in the GSIOs are multiplexed with GPIOs. Refer the chapter of GPIO for more information about these multiplexing. User can program what these multiplexed pins are used for. The GSIO block has 4 pins. SDO SDI SCK FRM the serial data output pin the serial data input pin the serial clock pin the frame pin
The base clock is generated dividing the GCLK by programming the GSIO control register GSCR. The SCK is generated from the basic clock in every data transfers. Using GSIO control field in the GSCR can program various types of serial interface. There are 5 control registers for GSIOs; GSCR0, GSCR1, GSCR2, GSCR3, and GSICR. The start time of transfer can be controlled with programming the delay counter field in the GSCRn. The base counter increments at every base clock right after writing the data into the GSDRn. The serial data starts to come out when delay counter value are same to base counter value. The word size of transfer can be programmed from 1 bit to 16 bits. The frame1 and the frame2 fields specify the start and end point of transition based on base counter. The frame polarity defines whether the frame signal is low active or high active signal. The Last Clock mask filed is for special serial interface, which makes the last clock pulse masked.
GCLK GSDI SIPO
/2
n Divider
divider factor n
base_clk
word_size
Counter
APB
GSDO SIPO GSCR
SCK Generator
frame1, frame2 Frame Coparator
GSFC
SDI SDO
SCK
FRM
Figure 11.1 GSIO Block Diagram
Preliminary
11-1
TCC76x
11.2 Register Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GSIO PORT
Table 11.1 GSIO Register Map (Base Address = 0x80000700) Name Address Type Reset Description GSDO0 GSDI0 GSCR0 GSGCR GSDO1 GSDI1 GSCR1 GSDO2 GSDI2 GSCR2 GSDO3 GSDI3 GSCR3 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x20 0x24 0x28 0x30 0x34 0x38 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Unknown Unknown 0x0000 0x0000 Unknown Unknown 0x0000 Unknown Unknown 0x0000 Unknown Unknown 0x0000 GSIO0 Output Data Register GSIO0 Input Data Register GSIO0 Control Register GSIO Global Control Register GSIO1 Output Data Register GSIO1 Input Data Register GSIO1 Control Register GSIO2 Output Data Register GSIO2 Input Data Register GSIO2 Control Register GSIO3 Output Data Register GSIO3 Input Data Register GSIO3 Control Register
GSIOn Output Data Register (GSDO0 ~ GSDO3) 31 30 29 28 27 26 25 24 23 22 0 15 14 13 12 11 10 9 8 7 6 GSDO[15:0] WORD
[19:16]
0x80000700 + (0x10 * n) 21 20 19 18 17 16 WORD[3:0] 5 4 3 2 1 0
GSIO word size
N GSIO data has (N+1) bit unit, N = 0 ~ 15 *) This field is valid only if WS of GSCRn register is set to 1. GSDO
[15:0]
Type R
GSIO Output Data The value that have been written through register is read The value is transmitted by LSB or MSB order that is controlled by MS field of GSCRn register.
GSDO
W
GSIOn Input Data Register (GSDI0 ~ GSDI3) 31 30 29 28 27 26 25 24 23 22 0 15 14 13 12 11 10 9 8 7 6 Data from GSIO Input Pin
21 5
0x80000704 + (0x10 * n) 20 19 18 17 16 4 3 2 1 0
By writing to GSDOn register, the corresponding GSIO block start to transmit and at the same time it starts to receive data through the SDI pin. At the end of transmission, the received data can be read through this GSDIn register. The bit order of receiving conforms to that of transmission.
Preliminary
11-2
TCC76x
GSIOn Control Register (GSCR0 31 30 29 28 27 26 MS EN WORD 15 14 13 12 11 10 0 DELAY FP EN
[31]
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GSIO PORT
0x80000708 + (0x10 * n) 21 20 19 18 17 16 DIV CP CM 5 4 3 2 1 0 FRM2
~ GSCR3) 25 24 23 WS 9 8 7 FRM1
22 6
0 1 MS
[30]
GSIO Enable Disable the corresponding GSIO block Enable the corresponding GSIO block First Bit Select Data is transmitted or received by LSB first order Data is transmitted or received by MSB first order
0 1
WORD [29:26] GSIO word size n GSIO data transaction has (n+1) bit unit, n = 0 ~ 15 *) This is valid only when the WS bit of GSCRn register is 0. WS [25] 0 1 DIV
[24:18]
Word Size Select GSIO word size is determined by WORD of GSCRn register GSIO word size is determined by BW of GSDO register GSIO base clock speed control Reserved. GSIO base clock has 1/(2n+2) of GCLK frequency. GSIO clock polarity SDO changes or SDI is sampled at SCK falling SDO changes or SDI is sampled at SCK rising Last clock mask No mask. GSIO clock is generated for every SDO. GSIO clock is masked at the last SDO period.
0 1 n 127 CP
[17]
0 1 CM
[16]
0 1
DELAY [14:13] Initial delay for serial transmission 0 Reserved. DELAY should not be set to 0. GSIO transmission starts after n base clock has generated. 1n3 FP
[12]
0 1 FRM1 [11:6] n FRM2 [5:0] n
Frame pulse polarity FRM has low active pulse FRM has high active pulse Frame pulse start position Frame pulse starts after n base clock has generated Frame pulse end position Frame pulse ends after n base clock has generated Preliminary 11-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GSIO PORT
Refer to the figure for a basic wave form of GSIO operation. GSIO Global Control Register (GSGCR) 31 30 29 28 27 26 25 24 0 15 G3 14 G2 13 G1 12 G0 11
IEN3
23 7
FLG3
22 6
FLG2
21 5
FLG1
20 4
FLG0
19 3
Busy3
0x8000070C 18 17 16 2
Busy2
10
IEN2
9
IEN1
8
IEN0
1
Busy1
0
Busy0
G[3:0] [15:12] if bit n is 1 (n=0~3)
GPIO_B[23:21] Other Function Signal Select FRM, SCK, SDO of GSIOn can be come out from GPIO_B[23:21]
*) If multiple bit of G[3:0] is set to 1, the output of each GSIO is ORed and come out from GPIO_B[23:21]. It is needed to configure the GPIO_B[23:21] as GSIO port to use these output.
IEN[3:0] [11:8] if bit n is 1 (n=0~3) 0
GSIO Interrupt Enable Enable GSIOn Interrupt Disable GSIOn Interrupt
*) The master flag to enable GSIO interrupt is GS bit of IEN register in interrupt controller. User must set that flag ahead as well as these fields.
FLG[3:0]
[7:4]
Type R W
if bit n is 1 (n=0~3)
GSIO Interrupt Flag Indicates that GSIOn operation (read/write) has been completed. Clear FLG[n] field
*) If an interrupt of a GSIO is enabled, GSIO interrupt is generated when the GSIO operation is completed. These FLGn can be used to distinguish which GSIO has generated the interrupt. These flags are cleared by writing "1" at the corresponding flag.
Busy[3:0] [3:0] if bit n is 0 if bit n is 1
GSIO Cycle Busy Flag Indicates that the transmission and reception of GSIOn have finished, and can process another serial data. Indicates that the transmission and reception of GSIOn is in operation, so it cannot process another serial data.
The following figures illustrate the representative waveforms about the various GSIO operations.
Preliminary
11-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GSIO PORT
div_factor = 1 ; div4 = 2*(1+1) word_size = 7 ; 8bits = 7+1 init_delay = 2, clk_pol = 0 frame_pol = 1 frame1 = 18, frame2 = 20 last_clk_mask = 0
GCLK 0 base clk SDO SCK FRM D0 D1 D2 D3 1 2 3 4 5 6 7 8 9 10 .... .... .... .... 14 15 16 17 18 19 20
D6
D7
clk_pol = 1
0 base clk SDO SCK FRM D0 D1 D2 D3 1 2 3 4 5 6 7 8 9 10 .... .... .... 14 15 16 17 18 19 20
D6
D7
frame1 = 17, frame2 = 19 last_clk_mask = 1, clk_pol = 1
0 base clk SDO SCK FRM D0 D1 D2 D3 1 2 3 4 5 6 7 8 9 10 .... .... .... 14 15 16 17 18 19 20
D6
D7
Figure 11.2 GSIO operation
Preliminary
11-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 GSIO PORT
Preliminary
11-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MISCELLANEOUS PERIPHERALS
12 MISCELLANEOUS PERIPHERALS 12.1 ADC
12.1.1 Overview The TCC76x has multiple-input general purpose low-power ADC for battery level detection, remote control interface, touch screen interface, etc. It is a CMOS type 10bit A/D converter with 8-channel analog input multiplexer. The TCC761 can support up to 8 inputs for ADC, and the other derivatives can support up to 3 inputs. * * * * * Resolution : 10-bit Maximum Conversion Rate : 500KSPS Main Clock : 2.5MHz (Max.) Standby Mode Input Range : 0.0V ~ VDDA_ADC
IRQ to Interrupt Controller ADCDATA/ ADCSTATUS Read Data Buffer (x4) Timing Control Command Buffer (x4) DO[9:0] EOC STC STBY CLK SEL[2:0]
APB
ADCCFG
ADC Core
AIN[7:0]
ADCCON/ ADCCONA
Figure 12.1 ADC Controller Block Diagram Except for the APB interface, the ADC controller module runs with ADCLK from the Clock Generator module. The clock input is always divided before sent to the ADC core. The EACLKmode register of Clock Generator and CLKDIV bits of ADCCFG register must be programmed to get desired frequency. The maximum frequency of CLK signal in Figure 12.1 must not exceed 2.5MHz. When one of the ADCCON or ADCCONA register is written with a channel number (SEL[2:0]), the SEL value is posted to the Command Buffer. The ADC Core starts conversion cycle as long as the Comand Buffer is not empty. After the conversion cycle is completed, the result is written in Read Data Buffer. The data can be read from either ADCDATA or ADCSTATUS register. Up to four different SEL values can be posted to the Command Buffer. When the buffer is full, data written to ADCCON/ADCCONA registers are ignored. Various operating options can be set by using ADCCFG register.
Preliminary
12-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MISCELLANEOUS PERIPHERALS
12.1.2 ADC Controller Register Description Table 12.1 ADC Controller Register Map (Base Address = 0x80000A00) Name Address Type Reset Description ADCCON 0x00 R/W 0x00000018 ADC Control Register ADCDATA 0x04 R Unknown ADC Data Register ADCCONA 0x80 R/W 0x00000018 ADC Control Register A ADCSTATUS 0x84 R/W Unknown ADC Status Register ADCCFG 0x88 R/W 0x00002400 ADC Configuration Register * ADCCON and ADCDATA registers are preserved for the TCC72x compatibility. For the new features in the TCC76x, ADCCONA and ADCSTATUS registers should be accessed.
ADC Control Register (ADCCON) 31 30 29 28 27 26 25 15 14 13 12 11 10 9 Reserved
24 23 Reserved 8 7
22 6
21 5
20 4 STB
19 3 X
0x80000A00 18 17 16 2 1 ASEL 0
STB [4] 1 0 ASEL [2:0] n
Type R/W
ADC Standby Select ADC goes to standby mode ADC starts operating
ADC Input Select ADINn pin is selected as ADC input signal n = 0 ~ 7 in TCC761. n = 0, 2, 4 in other derivatives. Refer to Pin Description 0x80000A04 18 17 16 2 1 0 FLG
ADC Data Register (ADCDATA) 31 30 29 28 27 26 25 15 14 13 0 12 11 10 9
24 0 8
23 7
22
21
20 4
19 3
6 5 ADATA
ADATA [10:1] ADC Data adc ADC data = adc *) All the AD input levels must be within the operable range that is from 0 V to VDDADC(the main power level of ADC). Do not exceed the limit. FLG [0] 1 0 ADC Status Flag Indicate that A/D conversion has finished, data is stable. A/D conversion is on processing, data is unstable
Preliminary
12-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MISCELLANEOUS PERIPHERALS
ADC Control Register A (ADCCONA) 0x80000A80 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved STB X ASEL *) This register has the same functionality as that of ADCCON register. Only the register address is different. ADC Status Register (ADCSTATUS) 31 30 29 28 27 26 25 24 R WBVCNT R RBVCNT 15 14 13 12 11 10 9 8 Reserved Bit 31 30:28 27 26:24 23:19 18:16 15:10 9:0 0x80000A84 18 17 16 RSELV 2 1 0
23 7
22
21 20 Reserved 6 5 4 RBDATA
19 3
Name R/W Reset Description Reserved R 0 WBVCNT R 0 Command Write Buffer Valid entry count. Up to 4 entries with different ASEL values can be posted to command buffer. Reserved R 0 RBVCNT R 0 Read Data Buffer Valid entry count. Up to 4 entries. Reserved R 0 RSEL R X Input channel number for current read data. Valid only if RBCNT is not zero. Reserved R 0 RBDATA R X Read Buffer Data. 0x80000A88 18 17 16 2 R8 1 APD 0 SM
ADC Configuration Register (ADCCFG) 31 30 29 28 27 26 25 24 23 22 Reserved 15 14 13 12 11 10 9 8 7 6 CLKDIV DLYSTC NEOC 0 Bit 15:12 11:8 7 6 5:4 3 2 1 Name CLKDIV DLYSTC NEOC Reserved FIFOTH IRQE R8 APD
21
20
19 3 IRQE
5 4 FIFOTH
0
SM
R/W Reset Description R/W 0x2 Clock Divisor Value. ADCLK is divided by ((CLKDIV + 1) * 2). R/W 0x4 Delay from SEL to STC (Start of Conversion) in ADC core CLK count. Whenever SEL value changes, delay is inserted. R/W 0 For test purpose only. Must be written as "0" R/W 0 R/W 0 FIFO Threshold for interrupt assertion. Interrupt will be asserted only if FIFOTH < (# of Valid Entry). R/W 0 Interrupt Enable. R/W 0 When this bit is "1", two LSBs are truncated. (shift right). Only "ADCSTATUS" register is affected by this bit. R/W 0 Auto Power Down Enable. This bit is effective only if SM bit (described below) is "1". After conversion cycle is done, the ADC core is forced to power down mode. R/W 0 Single Mode Enable. When disabled (0), ADC conversion cycle is repeated forever with the input selected by ASEL bits. When enabled (1), only one cycle is executed.
Preliminary
12-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MISCELLANEOUS PERIPHERALS
12.2 Miscellaneous Register Description
Table 12.2 Miscellaneous Register Map (Base Address = 0x80000A00) Name Address Type Reset Description USBCTR 0x14 R/W 0x00000004 USB Port Control Register TSTSEL 0x18 R/W 0x00000000 Test Mode Control Register MISCCFG 0x1C R/W 0x00000000 Miscellaneous Configuration Register CFGPUA 0x20 R/W 0x00000000 Pull-up Enable for GPIO_A CFGPUB 0x24 R/W 0x00000000 Pull-up Enable for GPIO_B CFGPUC 0x28 R/W 0x00000000 Pull-up Enable for GPIO_C CFGPUD 0x2C R/W 0x003C0000 Pull-up Enable for GPIO_D CFGDRVAL 0x30 R/W 0x00000000 Buffer Drive Strength Select AL CFGDRVAH 0x34 R/W 0x00000000 Buffer Drive Strength Select AH CFGDRVBL 0x38 R/W 0x00000000 Buffer Drive Strength Select BL CFGDRVBH 0x3C R/W 0x00000000 Buffer Drive Strength Select BH CFGDRVCL 0x40 R/W 0x00000000 Buffer Drive Strength Select CL CFGDRVCH 0x44 R/W 0x00000000 Buffer Drive Strength Select CH CFGDRVDL 0x48 R/W 0x00000000 Buffer Drive Strength Select DL CFGDRVDH 0x4C R/W 0x00000000 Buffer Drive Strength Select DH CFGDRVXL 0x50 R/W 0x03FFFFFF Buffer Drive Strength Select XL CFGDRVXH 0x54 R/W 0x04000000 Buffer Drive Strength Select XH CFGSYS 0x60 R/W 0x00000000 System Configuration * The base address is the same for the ADC controller. USB Port Control Register (USBCTR) 31 30 29 28 27 26 25 24 0 15 * 3 0 PSL USBCTR register is for test mode only, and must be set to 0x02 prior to use USB module. 14 13 12 11 10 9 8 7 6 5 4 2 1 0 CNT OVR OVC 0x80000A14 18 17 16
23
22
21
20
19
TEST Mode Register (TSTSEL) 31 30 29 28 27 26 15 * 14 13 12 11 10
25 9
24 0 8
23 7
22 6
21 5
20
19
0x80000A18 18 17 16
4 3 2 1 0 0 Reserved TSTSEL register is for test mode only, must be remained as 0x00. Preserved for the TCC72x compatibility.
Preliminary
12-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MISCELLANEOUS PERIPHERALS
Miscellaneous Configuration Register (MISCFG) 0x80000A1C Bit Name R/W Reset Description 31:16 Reserved R 0 15 RDYIRQEN R/W 0 READY Interrupt Request Enable. When enabled, input from READY pin can generate interrupt to the CPU via channel [15] of Interrupt Controller. MEN bit of Interrupt Enable Register is used for interrupt enable bit for READY pin only. Refer to RDY bits in Section 5.2 Interrupt Controller Register Description. 14 RDYIRQPOL R/W 0 READY Interrupt Request Polarity Control. (1 = inverted) 13:5 Reserved R 0 4 CIFEN R/W 0 Camera Interface Enable on to GPIO pins. CIFEN has a precedence over CFGI2C bit and GPIO control bits. Camera Interface Signals GPIO Pins HS GPIO_D[17] VS GPIO_D[16] CLK GPIO_D[15] Data[7:4] GPIO_D[21:18] Data[3:0] GPIO_A[3:0] 3:2 Reserved R 0 1:0 CFGI2C R/W 0 These bits selects GPIO pins for I2C signals. CIFEN CFGI2C[1:0] SCL SDA X 00 Disabled Disabled X 01 GPIO_A[9] GPIO_A[8] X 10 GPIO_A[11] GPIO_A[10] 0 11 GPIO_D[17] GPIO_D[16] 1 11 Disabled Disabled
Preliminary
12-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MISCELLANEOUS PERIPHERALS
The TCC76x supports programmable output drive strength and controllable pull-up resistor for the GPIO pins. For the external bus address and command signals, only the drive strength control is supported.
Control logic CFGDRVxH CFGDRVxL
Control bits f rom Buf f er Drive Strength Select A L/A H ~ DL/DH, XL/XH registers {DH,DL} Drive DH ====== ===== DL 00: 4mA 01: 6mA 10: 8mA 11: 12mA
PAD
Control bits f rom Pull-Up Enable A ~ D registers
CFGPUx
Figure 12.2 Pull-Up and Drive Strength Control
Note that pull-up and drive strength control is not applicable to GPIO_B[29:26] which are USB transceiver I/O pins.
Pull-Up Enable A (CFGPUA) Bit Name R/W Reset 31:0 CFGPUA R/W 0x00000000 Pull-Up Enable B (CFGPUB) Bit Name R/W Reset 31:0 CFGPUB R/W 0x00000000 Pull-Up Enable C (CFGPUC) Bit Name R/W Reset 31:0 CFGPUC R/W 0x00000000 Pull-Up Enable D Bit Name 31 CFGPUXD 30:0 CFGPUD (CFGPUD) R/W Reset R/W 0 R/W 0x003C0000
Description Pull-Up Enables for GPIO_A pins. Description Pull-Up Enables for GPIO_B pins. Description Pull-Up Enables for GPIO_C pins. Description Pull-Up Enable for XD[15:0] pins. Pull-Up Enables for GPIO_D pins.
0x80000A20
0x80000A24
0x80000A28
0x80000A2C
Buffer Drive Strength Select AL (CFGDRVAL) 0x80000A30 Bit Name R/W Reset Description 31:0 CFGDRVAL R/W 0x00000000 Buffer Drive Strength Select for GPIO_A pins. Buffer Drive Strength Select AH (CFGDRVAH) 0x80000A34 Bit Name R/W Reset Description 31:0 CFGDRVAH R/W 0x00000000 Buffer Drive Strength Select for GPIO_A pins. Buffer Drive Strength Select BL (CFGDRVBL) 0x80000A38 Bit Name R/W Reset Description 31:0 CFGDRVBL R/W 0x00000000 Buffer Drive Strength Select for GPIO_B pins.
Preliminary
12-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MISCELLANEOUS PERIPHERALS
Buffer Drive Strength Select BH (CFGDRVBH) 0x80000A3C Bit Name R/W Reset Description 31:0 CFGDRVBH R/W 0x00000000 Buffer Drive Strength Select for GPIO_B pins. Buffer Drive Strength Select CL (CFGDRVCL) 0x80000A40 Bit Name R/W Reset Description 31:0 CFGDRVCL R/W 0x00000000 Buffer Drive Strength Select for GPIO_C pins. Buffer Drive Strength Select CH (CFGDRVCH) 0x80000A44 Bit Name R/W Reset Description 31:0 CFGDRVCH R/W 0x00000000 Buffer Drive Strength Select for GPIO_C pins. Buffer Drive Strength Select DL (CFGDRVDL) 0x80000A48 Bit Name R/W Reset Description 31:0 CFGDRVDL R/W 0x00000000 Buffer Drive Strength Select for GPIO_D pins. Buffer Drive Strength Select DH (CFGDRVDH) 0x80000A4C Bit Name R/W Reset Description 31:0 CFGDRVDH R/W 0x00000000 Buffer Drive Strength Select for GPIO_D pins. Buffer Drive Strength Select XL (CFGDRVXL) 0x80000A50 Bit Name R/W Reset Description 31:28 Reserved R/W 0x0 Reserved 27 XDL R/W 0 Buffer Drive Strength Select for XD[15:0] pins 26 CLKL R/W 0 Buffer Drive Strength Select for SD_CLK pin 25 OEL R/W 1 Buffer Drive Strength Select for nOE pin 24 WEL R/W 1 Buffer Drive Strength Select for nWE pin 23:0 XAL R/W 0xFFFFFF Buffer Drive Strength Select for XA[23:0] pins. Buffer Drive Strength Select XH (CFGDRVXH) 0x80000A54 Bit Name R/W Reset Description 31:28 Reserved R/W 0x0 27 XDH R/W 0 Buffer Drive Strength Select for XD[15:0] pins 26 CLKH R/W 1 Buffer Drive Strength Select for SD_CLK pin 25 OEH R/W 0 Buffer Drive Strength Select for nOE pin 24 WEH R/W 0 Buffer Drive Strength Select for nWE pin 23:0 XAH R/W 0x000000 Buffer Drive Strength Select for XA[23:0] pins. System Configuration (CFGSYS) Bit Name R/W Reset 31:17 Reserved R/W 0x00000000 16 CFGRSPERR R/W 0 15:0 Reserved R/W 0x0000 Description 0x80000A60
Error Response Enable. When enabled, ABORT is asserted to the CPU if undefined addresses are accessed. Reserved for test. Must be written as zero.
Preliminary
12-7
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MISCELLANEOUS PERIPHERALS
Preliminary
12-8
TCC76x
13 DMA CONTROLLER 13.1 Overview
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DMA CONTROLLER
The TCC76x has 2-channel DMA controller for data transfer. The DMA can be used to perform high-speed transfers between external memory, on-chip memory, memory-mapped external devices, and on-chip peripheral module. It's possible to select channel priority levels with fixed priority or round-robin priority. The block diagram of DMA controller is in the following figure.
C H A N N E L0 C H A NN EL1 CHANNEL R e g is te rs E x te rn a l Request S e le c to r
EREQ 13
A H B I/F C o n tro l s ig n a l G e n e ra to r S o u rc e / D e s tin a to n A d d re s s G e n e ra to r
A H B
In te rru p t G e n e ra to r
IR Q
13 B U S D a ta B u ffe r ( 4 x 3 2 F ifo ) 13
ACK EOT
CHANNEL MUX
C H A N N E L A R B IT E R
Figure 13.1 DMA Controller Block Diagram
Preliminary
13-1
TCC76x
13.2 Register Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DMA CONTROLLER
C H A N N E L 0 C H A N N E L 1
Table 13.1 DMA Controller Register Map (Base Address = 0x80000E00) Name Address Type Reset Description ST_SADR0 0x00 R/W Start Address of Source Block SPARAM0 0x04/0x08 R/W Parameter of Source Block C_SADR0 0x0C R Current Address of Source Block ST_DADR0 0x10 R/W Start Address of Destination Block DPARAM0 0x14/0x18 R/W Parameter of Destination Block C_DADR0 0x1C R Current Address of Destination Block HCOUNT0 0x20 R/W 0x00000000 Initial and Current Hop count CHCTRL0 0x24 R/W 0x00000000 Channel Control Register CHCONFIG 0x2C R/W Channel Configuration Register ST_SADR1 0x30 R/W Start Address of Source Block SPARAM1 0x34/0x38 R/W Parameter of Source Block C_SADR1 0x3C R Current Address of Source Block ST_DADR1 0x40 R/W Start Address of Destination Block DPARAM1 0x44/0x48 R/W Parameter of Destination Block C_DADR1 0x4C R Current Address of Destination Block HCOUNT1 0x50 R/W 0x00000000 Initial and Current Hop count CHCTRL1 0x54 R/W 0x00000000 Channel Control Register
Start Source Address Register (ST_SADR) 0x80000E00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ST_SADR[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST_SADR[15:0] This register contains the start address of source memory block for DMA transfer. The transfer begins reading data from this address. Start Destination Address Register (ST_DADR) 0x80000E10 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ST_DADR[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ST_DADR[15:0] This register contains the start address of destination memory block for DMA transfer. Source Block Parameter Register (SPARAM) 31 30 29 28 27 26 25 24 23 22 SMASK[23:8] 15 14 13 12 11 10 9 8 7 6 SMASK[7:0] SMASK [31:8] 0 0x80000E04 / 0x80000E08 21 20 19 18 17 16 5 4 3 SINC[7:0] 2 1 0
Source Address Mask Register non-masked Masked so that source address bit doesn't be changed during DMA 1 transfer Each bit field controls the dedicated bit of source address field. That is, if SMASK[23] is set to 1, the 28th bit of source address is masked, and if SMASK[22] is set to 1, the 27th bit of source
Preliminary
13-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DMA CONTROLLER
address is masked, and so on. If a bit is masked, a corresponding bit of address bus is not changed during DMA transfer. This function can be used to generate circular buffer address. Source Address Increment Register Source address is added by amount of sinc at every write cycles. sinc is sinc represented as 2's complement, so if SINC[7] is 1, the source address is decremented. The addresses of DMA transfer have 32bit wide, but the upper 4bit of them are not affected during DMA transfer. If the source or destination address reaches its maximum address space like 0x7FFFFFFF or 0x2FFFFFFF, the next transfer is starting from 0x70000000 or 0x20000000 not from 0x80000000 or 0x30000000. Destination Block Parameter Register (DPARAM) 31 30 29 28 27 26 25 24 23 22 DMASK[23:8] 15 14 13 12 11 10 9 8 7 6 DMASK[7:0] DMASK [23:8] 0 0x80000E14 / 0x80000E18 21 20 19 18 17 16 5 4 3 DINC[7:0] 2 1 0 SINC [7:0]
Destination Address Mask Register non-masked Masked so that destination address bit doesn't be changed during DMA 1 transfer Each bit field controls the corresponding bit of source address field. That is, if DMASK[23] is set to 1, the 28th bit of source address is masked, and if DMASK[22] is set to 1, the 27th bit of source address is masked, and so on. If a bit is masked, a corresponding bit of address bus is not changed during DMA transfer. This function can be used to generate circular buffer address. Destination Address Increment Register Destination address is added by amount of dinc at every write cycles. dinc dinc is represented as 2's complement, so if DINC[7] is 1, the destination address is decremented. The addresses of DMA transfer have 32bit wide, but the upper 4bit of them are not affected during DMA transfer. If the source or destination address reaches its maximum address space like 0x7FFFFFFF or 0x2FFFFFFF, the next transfer is starting from 0x70000000 or 0x20000000 not from 0x80000000 or 0x30000000. Current Source Address Register (C_SADR) 0x80000E0C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C_SADR[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C_SADR[15:0] This register contains the current source address of DMA transfer. It represents that the current transfer read data from this address. This is read only register. Current Destination Address Register (C_DADR) 0x80000E1C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C_DADR[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 C_DADR[15:0] This register contains current destination address of DMA transfer. It represents that the current transfer write data to this address. This is read only register. DINC [7:0]
Preliminary
13-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DMA CONTROLLER
0x80000E20 18 17 16 2 1 0
HOP Count Register (HCOUNT) 31 30 29 28 27 26 25 15 14 13 12 11 10
24 23 22 C_HCOUNT[15:0] 9 8 7 6 ST_HCOUNT[15:0] Type R
21 5
20 4
19 3
C_HCNT [31:16] cn
Current Hop Count Represent cn number of Hop transfer remains
ST_HCNT [15:0] Type Start Hop Count sn R/W DMA transfers data by amount of sn Hop transfers At the beginning of transfer, the C_HCNT is updated by ST_HCNT register. At the end of every hop transfer, this is decremented by 1 until it reaches to zero. When this reaches to zero, the DMA finishes its transfer and may or may not generate its interrupt according to IEN flag of CHCTRL register. Channel Control Register (CHCTRL) 31 30 29 28 27 26 25 24 0 15 14 13 12 11 10 9 8
CONT
23 22 21 DMASEL[12:0] 7 6 5
BSIZE
20 4
19 3
FLAG
0x80000E24 18 17 16 2
IEN
1
REP
0
EN
0
SYNc
HRD
LOCK
BST
TYPE
WSIZE
DMASEL [28:16]
non-zero
Select Source of DMA Request Each bit field selects corresponding signal as a source for DMA request. The bit-map of this register is identical with the IEN of interrupt controller. So if you want to use EXINT0 pin as a source of DMA request, set DMASEL[0] as 1 and select transfer type of HW_ARBIT or HW_BURST. If multiple bits of this field are set, all the corresponding signal can generate DMA request for this channel. Issue Continuous Transfer DMA transfer begins from ST_SADR / ST_DADR address DMA transfer begins from C_SADR / C_DADR address It must be used after the former transfer has been executed, so that C_SADR and C_DADR contain a meaningful value. Hardware Request Synchronization Do not Synchronize Hardware Request. Synchronize Hardware Request. Hardware Request Direction ACK/EOT signals are issued when DMA-Read Operation. ACK/EOT signals are issued When DMA-Write Operation.
CONT [15] 0 1 SYNC [13] 0 1 HRD [12] 0 1
LOCK [11] Issue Locked Transfer 1 DMA transfer executed with lock transfer Lock field controls the LOCK signal (refer to AHB specification). When the LOCK is set to 1, the DMA transfer doesn't be bothered by other AHB masters like LCD controller, ARM etc. This field is only meaningful in case of non-burst type transfers.
Preliminary
13-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DMA CONTROLLER
BST[10] BURST Transfer 0 DMA transfer executed with arbitration. 1 DMA transfer executed with no arbitration. ( burst operation ) Arbitration means that at the end of every HOP transfer, the AHB bus is released from DMA channel so other master can occupy the bus when that master has requested the bus. Burst means that once the DMA request occurs, all of transfers are executed without further DMA requests. TYPE [9:8] Transfer Type 00 SINGLE transfer with edge-triggered detection 11 SINGLE transfer with level-sensitive detection 01 HW transfer 10 SW transfer In SINGLE Type, After one Hop data transferring DMA checks External DMA Request (DREQ ) and then if its bit is active , DMA transfers next hop data . DREQ is detected levelsensitive or edge-triggered by SINGLE transfer TYPE. The 1 Hop of transfer means 1 burst of read followed by 1 burst of write. 1 burst means 1, 2 or 4 consecutive read or write cycles defined by BSIZE field of CHCTRL register. The Figure 13.2 illustrates the relation among the above transfers.
DMA Transfer 1 Hop of Transfer 1 Burst of Read R R R R 1 Burst of Write W W W W R 1 Hop of Transfer 1 Burst of Read R R R 1 Burst of Write W W W W
* R : Read cycle for 8,16 or 32bit data * W : Write cycle for 8,16 or 32bit data * Arbitration Mode
Figure 13.2 Relation between Hop and Burst Transfers (If burst size is 4.) Hardware type transfer means that the DMA transfer triggered by external or internal hardware blocks selected by DMASEL field in CHCTRL register. This field has same mapping with interrupt enable flag of interrupt controller, so the DMA transfer can be occurred as like as interrupt is generated. Software type transfer means that the DMA transfer triggered by EN bit of CHCTRL Register . When this is set to 1, transfer request signal is generated internally and then the transfer begins immediately. Hardware demand type transfer (HW_DEMAND) means that once the DMA request occurs, DMA checks request signal each hop transfer, and if request signal is set, DMA transfer one hope's data. After transferring all hope's data, DMA operation will be finished. Figure 13.3 is the example of various types of transfer.
Preliminary
13-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DMA CONTROLLER
EREQ Transefer IDLE 1HOP WAIT 1HOP WAIT 1HOP WAIT
< SINGLE TRANSFER with edge-triggered >
EREQ Transefer IDLE 1HOP WAIT 1HOP WAIT 1HOP WAIT 1HOP WAIT
< SINGLE TRANSFER with Level Sensitive >
Transefer
IDLE
1HOP
WAIT
1HOP
WAIT
1HOP
WAIT
1HOP
WAIT
1HOP
< S(H)W TRANSFER with ARBitration >
Transefer
IDLE
1HOP
1HOP
1HOP
1HOP
1HOP
1HOP
1HOP
< S(H)W TRANSFER with Burst >
Figure 13.3 The Example Of Various Types of Transfer. BSIZE [7:6] 0 1 2, 3 WSIZE [5:4] 0 1 2, 3 FLAG [3] 1 1 Burst Size 1 Burst transfer consists of 1 read or write cycle. 1 Burst transfer consists of 2 read or write cycles 1 Burst transfer consists of 4 read or write cycles Word Size Each cycle read or write 8bit data Each cycle read or write 16bit data Each cycle read or write 32bit data Type R W DMA Done Flag Represents that all hop of transfers are fulfilled. Clears FLAG to 0
It does not automatically cleared by another transfer starts, so before starting any other DMA transfer, user must clear this flag to 0 for checking DMA status correctly. Interrupt Enable At the same time the FLAG goes to 1, DMA interrupt request 1 is generated. To generate IRQ or FIQ interrupt, the DMA flag of IEN register in the interrupt controller must be set to 1 ahead. IEN [2]
Preliminary
13-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DMA CONTROLLER
REP [1] 0
1
Repeat Mode Control After all of hop transfer has executed, the DMA channel is disabled The DMA channel remains enabled. When another DMA request has occurred, the DMA channel start transfer data again with the same manner (type, address, increment, mask) as the latest transfer of that channel. DMA Channel Enable DMA channel is terminated and disabled. It does not affect the HCOUNT register, so if the current hop counter is not zero when channel is disabled, it is possible that the transfer illegally starts right after channel is re-enabled. Make sure that HCOUNT is zero not to continue transfer after channel is re-enabled. DMA channel is enabled. If software type transfer is selected, this bit generates DMA request directly, or if hardware type transfer is used, the selected interrupt request flag generate DMA request. 0x80000E2C 18 17 16
MIS1 MIS0
EN [0]
0
1
Channel Configuration Register(CHCONFIG) 31 30 29 28 27 26 25 24 23 15 14 13 12 11 10 9
SWP1
8
SWP0
7
22 IS1 6
21 IS0 5
20 4
PRI
19 3
2
1
0
FIX
IS1 [22] Channel 1 Alternate interrupt status 0 No interrupt in channel 1 1 Channel1 Interrupt is occurred Without regard to Interrupt enable bit(IEN) of channel1, this bit indicates the channel1 interrupt status. This bit is automatically cleared when FLAG bit of channel1 is cleared. This bit is read only. IS0 [21] Channel 0 Alternate interrupt status 0 No interrupt in channel 0 1 Channel1 Interrupt is occurred Except for channel difference, This bit is the same as IS1 bit. MIS1[17] 0 1 Channel1 Masked Interrupt Status Masked interrupt is not occurred in channel 1 Channel1 Masked Interrupt is occurred
This bit is set when channel1 interrupt occurs and interrupt enable bit (IEN) of channel1 is set. This bit is automatically cleared when FLAG bit of channel1 is cleared. This bit is read only. MIS0[16] 0 1 Channel0 Masked Interrupt Status Masked interrupt is not occurred in channel 0 Channel0 Masked Interrupt is occurred
Except for channel difference, This bit is the same as MIS1 bit.
Preliminary
13-7
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 DMA CONTROLLER
SWP1 [9] 0 1
Channel1 SWAP Enable bit Do not Swap Channel1 Data. Swap Channel1 Data.
When this bit is set, data to be written to destination address will be swapped. For example, the 32bit source data which consists of 4bytes {D3,D2,D1,D0} will be stored {D0,D1,D2,D3} in destination address. The 16bit source data which consists of 2bytes {D1,D0} will be stored {D0,D1} in destination address. SWP0[8] 0 1 Channel0 SWAP Enable bit Do not Swap Channel0 Data. Swap Channel0 Data.
Except for channel difference, the function controlled by this bit is the same as its SWP1 bit. PRI[4] 0 1 PRIORITY CHANNEL0 is the Highest Priority in FIXed mode. CHANNEL1 is the Highest Priority in FIXed mode.
FIX [0] Fixed Priority Operation 0 Round-Robin (Cyclic) Mode. 1 Fixed Priority Mode. In round-robin mode, Each channel is enabled one by one every one hop transferring. In Fixed mode, according to PRI bit, the highest channel is serviced first and lower priority channel is serviced after higher priority channel operation is finished. See Figure 13.4 for more information.
CH1 IDLE 1HOP 1HOP CH1 END 1HOP CH0 CH0 END IDLE
< 2CHANNEL TRANSFER with Fixed Priority (channel 1 higher priority) >
CH0 IDLE 1HOP WAIT
CH1 1HOP WAIT
CH0 1HOP WAIT
CH1 1HOP WAIT
CH0 1HOP
< 2CHANNEL TRANSFER with Round Robin Priority >
Figure 13.4 Enabled 2Channel Transfer.
The CHANNEL1 Registers are not described in detail in this data sheet. The function of CHANNEL1 Registers are the same as CHANNEL0 Register except for channel difference and assigned address.
Preliminary
13-8
TCC76x
14 LCD CONTROLLER 14.1 Overview
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
The LCD controller (LCDC) is used to send out the image data from system memory to a LCD panel or NTSC/PAL encoder by properly formatting the raw image data stored in the memory. This LCDC provides all the necessary control signals to interface directly to mono STN, color STN, TFT panels, and NTSC/PAL encoders. Figure 14.1 shows LCDC block diagram and Figure 14.2 shows LCDC pin mappings. The features of the LCDC are: supports Thin Film Transistor(TFT) color displays with 16-bit interface supports Super Twisted Nematic(STN) displays with 4 or 8-bit interfaces 1, 2 or 4 bits per pixel(bpp) displays for mono STN 8 /16 bpp color displays for color STN 16 bpp true-color non-palletized color displays for color TFT resolution programmable up to 1024 * 1024 programmable timing for different display panels NTSC/PAL digital video encoder interface
interrupt controller
Register Bank Timing Controller LDMAC
HSYNC VSYNC PXCLK ACBIAS
BUS
AHB
Formatter
FIFO0 FIFO1 FIFO2 FIFO controller Pixel Serializer YUV to RGB Mixer
Gray scaler RGB to YUV
Output FIFO
PXD[15:0]
Figure 14.1 LCD controller Block Diagram Signal name HSYNC VSYNC PXCLK ACBIAS PXDATA[15:0] GPIO GPIO_B17 GPIO_B18 GPIO_B19 GPIO_B20 GPIO_A[31:16] Figure 14.2 PIN mapping
Preliminary
14-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
The following key parameters can be programmed: horizontal front and back porch horizontal synchronization pulse width number of panel clocks per line vertical front and back porch vertical synchronization pulse width number of lines per panel signal polarity panel clock frequency AC panel bias STN mono 1, 2, 4bpp STN color 8bpp(palletized, 256colors from 3375), 16bpp(direct 4:4:4RGB) STN 4 or 8-bit interface mode TFT LCD NTSC/PAL, Interlace/Non-interlace mode YUV2RGB, RGB2YUV Encoded pixel data are stored in off-chip memory in the frame buffer and are transferred to the LCDC's input FIFO, on a demand basis, using the AMBA AHB master interface. The LCDC issues a service request to the DMA after it has been initialized and enabled. The DMA automatically performs burst word transfers, filling empty entries of the FIFO. Values are fetched from the bottom of the FIFO, one entry at a time, and each 32-bit value is unpacked into individual pixel encodings, of 1, 2, 4, 8 or 16 bits each. After value is removed from the FIFO, the entries are invalidated. The frame buffer is in an off-chip memory area used to supply enough encoded pixel values to fill the entire screen one or more times. The pixel data buffer contains one encoded pixel values for each of the pixels present on the screen. The number of pixel data values depends on the size of the screen. Figure 14.4 shows the memory organization within the frame buffer for each size pixel encoding.
14.2 Related Blocks
Before using LCDC, it needs to configure blocks which are related to LCDC. First, timing control signals and pixel data signals of LCDC use GPIO_B[20:17] and GPIO_A[31:16]. Figure 14.2 shows GPIO mapping. Therefore, these GPIO ports must be configured to LCD function and output mode. GPIO part explains these configurations in detail. Figure 14.3 shows output pixel data organization on GPIO[31:16]. Second, LCLK, which is the main clock of LCDC, must be enabled and configured to the proper frequency. HCLK frequency must be higher than LCLK frequency. Otherwise, FIFO underrun is occurred. In case of FIFO underrun, HCLK frequency must be set to faster value and/or LCLK frequency must be set to slower value.
Preliminary
14-2
TCC76x
STN PXDW=0(4bits) STN PXDW=3(8bits)
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
15 14 13 12 11 10 X 15 14 13 12 11 10 X
9
8
7
6
5
4
3
21 PD[3:0] 2 1
0
9
8
7
6
5
43 PD[7:0]
0
TFT PXDW=2(6bits) TFT PXDW=3(8bits) TFT PXDW=4(565)
15 14 13 12 11 10 X 15 14 13 12 11 10 X 15 14 13 12 11 10 R[4:0]
9
8
7
6
5 43210 R[5:0], G[5:0], B[5:0]* 5 4321 R[7:0], G[7:0], B[7:0]* 5 4 3 21 B[4:0] 0
9
8
7
6
*)R->G->B
9
87 G[5:0]
6
0
TV 15 14 13 12 11 10 PXDW=3(8bits) X TV 15 14 13 12 11 10 PXDW=6(16bits) Y[7:0]
9
8
765 43210 U0[7:0], Y0[7:0], V0[7:0], Y1[7:0]**
**)U0->Y0->V0->Y1
9
8
7
6
5 432 U[7:0], V[7:0]***
1
***
0
)U->V
Figure 14.3 Output Pixel Data Organization(GPIO_A[31:16] = PXDATA[15:0])
14.3 Interrupt configuration
LCDC has three maskable interrupt sources; Disable Done(DD), Register Update(RU), and FIFO underrun interrupt(FU). Each interrupt source can be masked as corresponding bit of LIM is set to 1. DD interrupt is generated when LEN bit is cleared and current frame is completed. RU interrupt is generated after all of control registers are updated. So, control registers which was programmed are applied to displaying a frame after displaying the current frame is completed. FU interrupt is generated when FIFO underrun is occurred. HCLK frequency is always faster than LCLK frequency to prevent FIFO underrun from taking place. For using LCDC interrupt, all of LCDC interrupt source must be cleared before enabling interrupt. The corresponding bits of LSTATUS are written to 1 to clear it. And CREQ register of interrupt controller must be also cleared. 1. clear LSTATUS register of LCDC 2. clear CREQ of interrupt controller 3. set LIM register of LCDC to unmask the corresponding LCDC interrupt. 4. set IEN register of interrupt controller to enable the LCDC interrupt Whenever LCDC interrupt is generated, the corresponding bits of LSTATUS register must be cleared. Otherwise, LCDC interrupt is not generated any more.
Preliminary
14-3
TCC76x
14.4 STN LCD
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
The LCDC generates VSYNC, HSYNC, PXCLK, ACBIAS, and PXDATA signals for STN LCD driver.
Figure 14.4 shows 1bpp, 2bpp, 4bpp, 8bpp, and 16bpp of PXDATA memory organization. BR of LCTRL register indicates whether pixel data in frame memory is bigendian for 1bpp, 2bpp, or 4bpp mode. Figure 14.5 shows RGB configuration for color STN LCD. The timing diagram for STN mode is shown in Figure 14.7. VSYNC and HSYNC pulse are controlled by the configurations of the LPC field of LHTIME and FLC field of LVTIME1 and LVTIME2. Each field is related to the LCD size and display mode. In 1bpp, 2bpp, 4bpp: LPC In 8pp and 16bpp (RGB): LPC =(Horizontal display size / pixel data width) - 1 = {3 * Horizontal display size / (pixel data width) - 1}
Pixel data width is determined by PXDW of LCTRL register. In the case of STN LCD mode, it must be 4 or 8-bit width.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 1BPP p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16 2BPP p15 p14 p13 p12 p11 p10 p9 p8 4BPP p7 p6 p5 p4 8BPP p3 p2 16BPP p1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1BPP p15 p14 p13 p12 p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 2BPP p7 p6 p5 p4 p3 p2 p1 p0 4BPP p3 p2 p1 p0 8BPP p1 p0 16BPP p0
a) BR=0
Preliminary
14-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
1BPP 2BPP 4BPP 8BPP 16BPP
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 p24 p25 p26 p27 p28 p29 p30 p31 p16 p17 p18 p19 p20 p21 p22 p23 p12 p13 p14 p15 p8 p9 p10 p11 p6 p7 p4 p5 p3 p2 p1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 p8 p9 p10 p11 p12 p13 p14 p15 p0 p1 p2 p3 p4 p5 p6 p7 p4 p5 p6 p7 p0 p1 p2 p3 p2 p3 p0 p1 p1 p0 p0
1BPP 2BPP 4BPP 8BPP 16BPP
b) BR=1 Figure 14.4 STN LCD pixel data organization
STN 8BPP STN 16BPP 15 14 13 12 11 10 9 X R[3:0] 8 76 R[1:0] 7 5 43 G[2:0] 4 3 2 1 0 B[2:0] 0
65 G[3:0]
21 B[3:0]
Figure 14.5 Color STN Pixel Data ACBIAS signal is used by the LCD driver to alternate the polarity of the row and column voltage used to turn the pixel on and off. It is controlled by the ACDIV field of LCLKDIV register. This value must be (lpw+1) times. ACDIV = {(lpw+1) * n} -1 n = number of HSYNC(CL1) PXCLK frequency is determined by the CLKDIV field of LCLKDIV register as follows. The minimum value of CLKDIV is 3 in STN mode. fPXCLK = fLCLK / (2 * CLKDIV) (1)
VSYNC frequency is related to the field of FEWC, LSWC, LEWC, LPC, and FLC as well as LCLK and PXCLK. fVSYNC = fPXCLK / [{(LPW+1) + (LPC+1) + (LSWC+1) + (LEWC+1)} * {(FLC + 1) + (FPW+1)}]
Therefore, if FR is the required refresh rate, fPXCLK_REQ, which is the required PXCLK, is the flowing. fPXCLK_REQ = FR x [ {(LPW+1) + (LPC+1) + (LSWC+1) + (LEWC+1)} * {(FLC + 1) + (FEWC+1)} ] (2) The LCDC contains dithering pattern registers for STN LCD: a 48-bit modulo 7 dithering pattern register (LDP7L and LDP7H), a 32-bit modulo 5 dithering pattern register (LDP5), a 16-bit modulo 4 dithering pattern register (LDP4), and a 16-bit modulo 3(LDP3) dithering pattern register. These dithering pattern registers can contain the programmable Preliminary 14-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
pre-dithered pattern values for each duty cycle ratio. Bits per pixel of image determines pre-dithered value. If BPP is 4 or 16, pre-dithered value is non-palettized value, which is pixel data in the frame memory. If BPP is 2, a nibble of LUTBL that is indexed by 2-bit pixel data is predithered value. If BPP is 8, each nibble of LUTRD, LUTGR, and LUTBL that is indexed by pixel data, which consist of 3-bit R, 3-bit G, and 2-bit B, is pre-dithered value. Figure 14.6 shows the relationship between pre-dithered values and dithering pattern registers. The LDP7H and LDP7L contain 5 pre-dithered patterns for 1/7, 3/7, 4/7, 5/7, and 6/7 duty cycle rate. Each field of LDP7H and LDP7L is 7-bit long. The LDP5 has 4 pre-dithered pattern fields for 1/5, 2/5, 3/5, and 4/5 duty cycle rate. Each field of LDP5 is 5-bit long. The LDP4 has 3 pre-dithered pattern fields for 1/4, 1/2(=2/4), and 3/4 duty cycle rate, and each field is 4-bit long. Likewise, the LDP3 has 2 fields for 1/3 and 2/3 duty cycle rate with 3-bit length. Note that the pre-dithered data for 1 and 0 is not defined in the dithering pattern register, because these values are implemented with VDD and VSS condition. Pre-dithered value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Dithering register Duty cycle ratio 0 0 DP1_7 1/7 DP1_5 1/5 DP1_4 1/4 DP1_3 1/3 DP2_5 2/5 DP3_7 3/7 DP2_4 1/2 DP4_7 4/7 DP3_5 3/5 DP2_3 2/3 DP5_7 5/7 DP3_4 3/4 DP4_5 4/5 DP6_7 6/7 1 1 Figure 14.6 Dithering operation
Preliminary
14-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
ACDIV ......
VSYNC
HSYNC
......
ACBIAS
......
PD
line0
line1
line 2 ......
line n
line0
FLC + 1 LPW + 1
FEWC + 1
LPC + 1
VSYNC
HSYNC
PXCLK
PD LSWC + 1
line0 LEWC + 1
line1
line2
Figure 14.7 STN mode timing
Preliminary
14-7
TCC76x
Example
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
For a monochrome STN LCD, 4-bit interface panel, 4 pixels are captured by the panel in every panel clock cycle. Figure 14.8 gives the major registers to be programmed for supporting 4-bit interface STN LCD. LCLK and Refresh rate are examples only. And LSWC, LEWC, LPW, and FEWC are STN LCD panel dependent. LCLK = 20 MHz, Refresh rate = 60 Hz PXDW* = 0 (4bits) VD* = 1 BPP* = 2 (4bpp) DP* = 0 (one pixel data per pixel clock cycle) NI = 1 TV* = 0, TFT* = 0, STN* = 1 LSWC* = LEWC* = LPW* = FEWC* = 1 (STN LCD dependent) Width (pixel) 160 160 Height (pixel) 160 200 LPC* 39 39 FLC* 159 199 DHSIZE* DVSIZE* 160 160 160 200 F**
PXCLK_REQ
CLKDIV* fPXCLK*** 25 20 0.4 0.5
0.393 0.491
320 200 79 199 320 200 0.973 10 1 .*) control registers to be programmed. **) Refer to expression (2). ***) Refer to expression (1). Figure 14.8 Monochrome STN LCD(4bits, 1BPP) example
Preliminary
14-8
TCC76x
14.5 TFT LCD
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
The LCDC supports 16bpp true-color non-palletized color displays for color TFT LCD. Figure 14.9 show frame memory organization. If image source is YUV420 or YUV422, YUV2RGB converer can be used as Y2R of LCTRL is set. And each YUV channel is indicated by LIBA0, LIBA1, and LIBA2 register. It generates the control signals for LCD driver such as, VSYNC, HSYNC, PXCLK, PXDEN(ACBIAS) and PXDATA. Figure 14.10 shows PXDATA format in TFT mode. The timing diagram of TFT mode is shown in Figure 14.12.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R1[4:0] G1[4:0] B1[4:0] RGB555 I* R1[4:0] G1[5:0] B1[4:0] RGB565 U6 or V6 U4 or V4 8BPP(U or V) 8BPP(Y) Y3 Y2
15 14 13 12 11 10 R0[4:0] RGB555 I* RGB565 R0[4:0] U2 or V2 8BPP(U or V) 8BPP(Y) Y1
9
76 G0[4:0] G0[5:0]
8
5
21 B0[4:0] B0[4:0] U0 or V0 Y0
4
3
0
Figure 14.9 TFT LCD pixel data memory organization
PXDW 15 14 13 12 11 10 565 R[4:0] PXDW 15 14 13 12 11 10 555 I* R[4:0] 9 87 G[5:0] 8 6 5 4 3 21 B[4:0] 21 B[4:0] 0
9
76 G[4:0]
5
4
3
0
*) intensity bit Figure 14.10 TFT LCD output pixel data The VSYNC and HSYNC frequency is controlled by the LPC and FLC field. LPC = (Horizontal display size) - 1 FLC = (Vertical display size) - 1 And PXCLK frequency is determined by the CLKDIV value. fPXCLK = fLCLK / (2 x CLKDIV) (3)
The frequency of VSYNC signal is the frame rate. So the frame rate can be calculated as follows: fVSYNC = fPXCLK / [ (FSWC + FPW + FLC +FEWC) x {(LSWC+1) + (LPC+1) + (LEWC+1) + (LPW+1)}] Therefore, if FR is the required refresh rate in TFT mode, fPXCLK_REQ, which is the required PXCLK, is the flowing. fPXCLK_REQ = FR x {(LPW+1) + (LPC+1) + (LSWC+1) + (LEWC+1)} x {(FSWC+1) + (FPW+1) + (FLC+1) +(FEWC+1)} (4) Preliminary 14-9
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
Example
TFT LCD(RGB565), LCLK = 80MHz and Refresh rate = 60Hz, PXDW* = 0x4, YUV* = 0, BPP* = 0x4, DP* = 0, NI* = 1 TV* = 0, TFT* = 1, STN* = 0 LSWC* = LEWC* = LPW* = 3 (TFT LCD dependent) FSWC* = FEWC* = FPW* = 1 (TFT LCD dependent) Width (pixel) Height (pixel) LPC* FLC* DHSIZE* DVSIZE* F**
PXCLK_REQ
CLKDIV* fPXCLK***
176 220 175 219 176 220 2.55 15 2.67 240 320 239 319 240 320 4.93 8 5 640 480 639 479 640 480 19.01 2 20 .*) control registers to be programmed. **) Refer to expression (4). ***) Refer to expression (3). Figure 14.11 TFT LCD(RGB565) example
FPW+1 VSYNC HSYNC
FSWC+1
FLC+1
FEWC+1
PXDATA ACBIAS LPW+1 HSYNC LSWC+1
line 0
line 2
......
line n-1
line n
LPC +1
LSWC+1
PXCLK
PXDATA
line 0
ACBIAS
Figure 14.12 TFT mode timing
Preliminary
14-10
TCC76x
14.6 NTSC/PAL interface
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
The LCDC can generate the control signals for 8-bit or 16-bit NTSC/PAL encoder. The pixel color mapping of NTSC/PAL mode is identical to that of 8-bit or 16-bit LCD interfacing. For NTSC/PAL interface, TV field of LCTRL register must be set. Registers used in this mode are similar to those in TFT mode except for LVTIME1 and LVTIME2 registers.; LVTIME1 is for odd field and LVTIME2 is for Even field. And these registers value is not based on HSYNC, but based on half of HSYNC. For example, if FPW of LVTIME1 is 3, pulse width of VSYNC on odd field is not 4 HSYNC cycles, but 2 HSYNC cycles. And if FPW of LVTIME1 is 4, it represents to 2.5 HSYNC cycles. Interlace/Non-interlace mode can be configured by NI field of LCTRL register. Figure 14.13 and Figure 14.14 each show the timing diagram of NTSC and PAL interlace mode. In non-interlace mode, odd field sync signals are repeated instead.
(LVTIME4.FEWC+1)/2 (LVTIME1.FPW +1)/2 Odd Field ...... (LVTIME3.FPW + 1)/2 Even Field
VSYNC
1 HSYNC
2
3
4
5
6
7
8
......
265
266
267
268
268
(LVTIME2(odd) or 4(even).FSWC + 1)/2 ...... LPW + 1
VSYNC
LPC + 1
HSYNC
......
...... PXCLK
...... ACBIAS
PXDATA
line 0
line 1
LSWC+1
LEWC+1
Figure 14.13 NTSC interlace mode timing
Preliminary
14-11
TCC76x
(LVTIME4.FEWC+1)/2
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
(LVTIME1.FPW+1)/2 Odd Field ......
(LVTIME3.FPW+1)/2 Even Field
VSYNC
...... HSYNC
(LVTIME2(odd) or 4(even).FSWC + 1)/2 VSYNC LPW + 1 ......
LPC + 1 ......
HSYNC
...... PXCLK
...... ACBIAS
PD
line 0
line 1
LSWC + 1
LEWC + 1
Figure 14.14 PAL interlace mode timing
Example
The frame memory has RGB565 type image source. The following code fragment gives the major registers to be programmed for NTSC encoder interface. HCLK = 72MHz, LCLK = 54MHz, PXCLK=27MHz LCTRL = 0x041E8E03 LCTRL.YUV = 0 (RGB) LCTRL.BPP = 0x4 (RGB565) LCTRL.R2Y = 0x1 LCTRL.DP = 0x1 LCTRL.PXDW = 0x6 (16bits) LCTRL.TV = 0x1 LCTRL.IAC = 0x0 LCTRL.IVS = 0x1 LCTRL.IHS = 0x1 LCTRL.IPX = 0x1 LCTRL.NI = 0x0 LCTRL.DEN = 0x1
Preliminary
14-12
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
LCTRL.LEN = 0x1 LCLKDIV = 1 LHTIME1.LPW = 128-1 LHTIME1.LPC = 1440-1 LHTIME2.LSWC = 116-1 LHTIME2.LEWC = 32-1 LVTIME1.FPW = 3*2 -1 LVTIME1.FLC = 240*2 - 1 LVTIME2.FSWC = 15*2 -1 LVTIME2.FEWC = 4*2+1 -1 LVTIME3.FPW = 3*2-1 LVTIME3.FLC = 240*2 -1 LVTIME4.FSWC=15*2+1-1 LVTIME4.FEWC=4*2-1 LIP.X = 0 LIP.Y = 0 LIS.WIDTH = LDS.VSIZE = 720 LIS.HEIGHT = LDS.HSIZE = 480
(LVTIME1.FPW+1)/2 (LVTIME2.FSWC+1)/2 (LVTIME1.FLC+1)/2 (LVTIME2.FEWC+1)/2
(LVTIME3.FPW+1)/2
(LVTIME4.FSWC+1)/2
(LVTIME3.FLC+1)/2
(LVTIME4.FEWC+1)/2
717
718
719
716
718
718
LHTIME1.LPW+1
LHTIME2.LSWC+1
LHTIME1.LPC+1
LHTIME2.LEWC+1
Figure 14.15 Example: NTSC interlace mode timing diagram
Preliminary
14-13
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
14.7 Register Description
Name LCTRL LCLKDIV LHTIME1 LHTIME2 LVTIME1 LVTIME2 LVTIME3 LVTIME4 LLUTRD LLUTGR LLUTBL LDP7L LDP7H LDP5 LDP4 LDP3 LDS LSTATUS LIM LIP LIS LIBA0 LICA0 LIBA1 LIBA2 Table 14.1 LCD Controller Register Map (Base Address = 0x80000F00) Address Type Reset Description 0x00 R/W 0x00000006 control register 0x04 R/W 0x00000000 ac-bias clock and pixel clock divisor 0x08 R/W 0x00000000 Horizontal axis timing control register1 0x0C R/W 0x00000000 Horizontal axis timing control register2 0x10 R/W 0x00000000 Vertical axis timing control register1 0x14 R/W 0x00000000 Vertical axis timing control register2 0x18 R/W 0x00000000 Vertical axis timing control register3 0x1C R/W 0x00000000 Vertical axis timing control register4 0x20 R/W 0x00000000 Lookup table for red color 0x24 R/W 0x00000000 Lookup table for green color 0x28 R/W 0x00000000 Lookup table for blue color 0x2C R/W 0x4D2B3401 modulo 7 dithering pattern low register 0x30 R/W 0x0000003F modulo 7 dithering pattern high register 0x34 R/W 0x1D0B0610 modulo 5 dithering patterns 0x38 R/W 0x00000768 modulo 4 dithering patterns 0x3C R/W 0x00000034 Modulo 3 dithering patterns 0x40 R/W 0x00000000 Display size register 0x44 R/Clear 0x00000000 Status register 0x48 R/W 0x00000007 Interrupt mask register 0x4C R/W 0x00000000 Image position register 0x50 R/W 0x00000000 Image size register 0x54 R/W 0x00000000 Image base address register 0 0x58 R 0x00000000 Image current address register 0x5C R/W 0x00000000Image base address register 1 0x60 R/W 0x00000000 Image base address register 2
Preliminary
14-14
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
0x80000F00 18 17 16 PXDW[2:0] 2 1 0
DEN LEN
LCD Control Register (LCTRL) 31 30 29 28 27 26 25 YUV[1:0] BPP[3:0] 15 14 13 12 11 10 9
TV IAC IVS IHS IPX
24 8
23 7
NI
22 BR 6
21 20 Y2R R2Y 5 4
TFT
19 DP 3
STN
YUV
[29:28]*
YUV data type RGB YUV 4:2:0 YUV 4:2:2 *) When it is YUV 4:2:0 or YUV 4:2:2, BPP must be 8bpp. Bits Per Pixel 1 bpp 2 bpp 4 bpp 8 bpp* RGB565 RGB555 RGB444 (STN only) *) When it is YUV 4:2:0 or YUV 4:2:2, BPP must be 8bpp. Bit-Reverse
00 01 11
BPP [27:24] 0000 0001 0010 0011 0100 0101 0111
BR[22]* 0 1
Little-endian pixel data Big-endian pixel data *) It is only used when BPP is 1, 2, or 4bpp.
Y2R[21] 0 1 R2Y[20] 0 1 DP[19] 0 1
YUV to RGB converter Disable Enable RGB to YUV converter Disable Enable Double Pixel Data One pixel data every one PXCLK cycle is output. One pixel data every two PXCLK cycle is output. It is for 16-bit TV mode. Pixel Data Width 4 bits 6 bits 8bits 16bits(RGB565) 16bits(RGB555) 16bits(YUV) Inverted ACBIAS signal Normal Inverted
PXDW [18:16] 000 010 011 100 101 110 IAC [12] 0 1
Preliminary
14-15
TCC76x
IVS [11] 0 1 IHS[10] 0 1 IPX 0 1 NI
[7] [9]
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
Inverted VSYNC signal Normal Inverted Inverted HSYNC signal Normal Inverted Inverted Pixel Clock Data is driven onto the LCD's data pins on the rising edge of pixel clock pin Data is driven onto the LCD's data pins on the falling edge of pixel clock pin Non-interlace Interface mode. Odd field timing control: LVTIME1, LVTIME2 Even field timing control: LVTIME3, LVTIME4 Non-interlace mode LVTIME1 and LVTIME3 must be same, and LVTIME2 and LVTIME4 must be same. TFT [4] 0 1 STN 1 0
[3]
0
1
Description Select STN-LCD mode Select TFT-LCD mode Select TV mode In this mode, all values of LVTIMEn registers are divided by 2. Therefore, if 1 0 0 LVTIME1.FPW is set to 5 HSYNC cycles, LVTIME1.FPW is programmed to 9(= 5*2 - 1). Other combinations are undefined and should not be used. DEN 0
[1]
TV[15] 0 0
Pixel Data Transfer Enable
Disable If LEN is enabled, LCD controller only generates timing control signals. 1 Enable Normally, DEN must be always enabled to operate LCD controller and display pixel data on LCD. Some LCD modules, however, have their own frame memory. In this case, if the current frame is the same with previous frame, it needs not to be transferred to LCD module for reducing power-consumption and bus-bandwidth. LEN [0] 0 1 LCD controller Enable Disable Enable 0x80000F04 18 17 16 2 1 0
LCD Clock Divider Register (LCLKDIV) 31 30 29 28 27 26 25 24 0 15 14 13 12 11 ACDIV 10 9 8
23 7
22 6
21 5
20
19
4 3 CLKDIV
Preliminary
14-16
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
FIELD ACDIV [15:8]
CLKDIV [7:0]
Description AC Bias clock divisor(STN only). The number of clock cycles to count between each toggle of AC_BIAS pin.. ACBIAS is toggled every n HSYNC cycles if ACDIV is {(lpw+1) *n - 1}. Pixel clock divisor Note that programming CLKDIV less than 3 is illegal for STN LCD. PXCLK = LCLK / (2*CLKDIV) (if CLKDIV = 0, PXCLK = LCLK) 0x80000F08 18 17 16 2 1 0
LCD Horizontal Timing Register1 (LHTIME1) 31 30 29 28 27 26 25 24 23 0 15 14 13 0 12 11 10 9 8 7
22 6
21 5 LPC
20 19 LPW 4 3
FIELD LPW [23:16]
LPC [10:0]
Description Line Pulse Width is the number of pixel clock cycles. Line Pulse Count is the number of pixel clock cycles in each line minus 1 on the screen TFT /NTSC(16bit)/PAL(16bit) : active horizontal pixels - 1 Color STN : (3 * Horizontal display size / pixel width) -1 Mono STN: (Horizontal display size / pixel width )- 1 0x80000F0C 22 6 21 5 20 19 LSWC 4 LEWC 3 18 2 17 1 16 0
LCD Horizontal Timing Register2 (LHTIME2) 31 15 30 14 29 13 28 0 12 0 27 11 26 10 25 9 24 8 23 7
FIELD LSWC [24:16] LEWC [8:0]
Description Line Start Wait Cycle is the number of dummy pixel-clock cycles minus 1 to insert from the start of each horizontal line of pixels. Line End Wait Cycle is the number of dummy pixel-clock cycles minus 1 to insert before the end of each horizontal line of pixels.
Preliminary
14-17
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
0x80000F10
LCD Vertical Timing Register1 (LVTIME1) 31 15 30 14 29 13 0 28 12 27 0 11 10 9 8 7 6 5 FLC 4 26 25 24 23 22 21 20
19 18 FPW 3 2
17 1
16 0
FIELD FPW [21:16] FLC [10:0]
Description TFT/TV : Frame Pulse Width is the pulse width of frame clock (VSYNC). STN: N/A Frame Line Count is the number of lines in each frame on the screen.
LCD Vertical Timing Register2 (LVTIME2) 31 30 29 28 27 26 25 24 23 0 15 14 13 12 0 11 10 9 8 7
22 6
21 20 FSWC[8:1] 5 4 FEWC
19 3
0x80000F14 18 17 16 VD 2 1 0
FIELD FSWC [8:1] VD
FEWC [7:0]
Description TFT/TV: Frame Start Wait Cycle is the number of lines to insert at the end of each frame. VD is FSWC[0]. STN: FSWC[8:1] is N/A. If VD is set, VSYNC signal starts on negative falling edge of HSYNC. TFT/TV: Frame End Wait Cycle is the number of lines to insert at the beginning of each frame. STN: extra dummy lines between the end and beginning of frame 0x80000F18 19 18 17 16 FPW
LCD Vertical Timing Register3 (LVTIME3) 31 30 29 28 27 26 25 24 23 0 15 14 13 0 12 11 10 9 8 7
22 6
21
20
5 4 3 2 1 0 FLC If NI of LCTRL is 0, LVTIME3 and LVTIME4 is for even-field. Otherwise, LVTIME3 and LVTIME4 must be the same with LVTIME1 and LVTIME2. 0x80000F1C 18 17 16 2 1 0
LCD Vertical Timing Register4 (LVTIME4) 31 30 29 28 27 26 25 24 23 0 15 14 13 12 0 11 10 9 8 7
22 6
21 5
20 19 FSWC 4 FEWC 3
Preliminary
14-18
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
0x80000F20 21 5 20 4 19 3 18 2 17 1 16 0
LCD Lookup Register for RED (LLUTRD) 31 15 30 14 29 13 28 12 27 11 26 10 25 24 23 22 LLUTRD[31:16] 9 8 7 6 LLUTRD[15:0]
This register is used for supporting palletized color STN-LCD. It is divided into 8 nibbles. The passive color mode uses a lookup table register, which allows any 8 red levels to be selected out of the 16 possible red levels. The most significant 3-bit of 8-bit encoded pixel addresses 8 red palette locations. Note that LLUTRD register is only used in STN-LCD mode LCD Lookup Register for GREEN (LLUTGR) 31 30 29 28 27 26 25 24 23 22 LLUTGR[31:16] 15 14 13 12 11 10 9 8 7 6 LLUTGR[15:0] 0x80000F24 18 17 16 2 1 0
21 5
20 4
19 3
This register is used for supporting palletized color STN-LCD. It is divided into 8 nibbles. The passive color mode uses a lookup table register, which allows any 8 green levels to be selected out of the 16 possible green levels. The next most significant 3-bit of 8-bit encoded pixel addresses 8 green palette locations. Note that LLUTGR register is only used in STN-LCD mode LCD Lookup Register for BLUE (LLUTBL) 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 0x80000F28 18 17 16 2 1 0
23
22
21 5
20 4
19 3
0 8 7 6 LLUTBL[15:0]
This register is used for supporting palletized color STN-LCD. It is divided into 4 nibbles. The passive color mode uses a lookup table register, which allows any 4 blue levels to be selected out of the 16 possible blue levels. The least significant 2-bit of 8-bit encoded pixel addresses 4 green palette locations. Note that LLUTBL register is only used in STNLCD mode.
Preliminary
14-19
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
0x80000F2C
LCD Dithering Pattern Register (LDP7L) 31 0 15 0 30 14 29 13 28 12 27 26 DP5_7 11 10 DP3_7 25 9 24 8 23 0 7 0 22 6 21 5 20 4
19 18 DP4_7 3 DP1_7 2
17 1
16 0
LCD Dithering Pattern Register (LDP7H) 31 30 29 28 27 26 25 24 0 15 14 13 12 11 0 10 9 8
23 7
22 6
21 5
20 4
19 3 DP6_7
0x80000F30 18 17 16 2 1 0
LCD Dithering Pattern Register (LDP5) 31 30 29 28 27 26 25 24 0 DP4_5 15 14 13 12 11 10 9 8 0 DP2_5 LCD Dithering Pattern Register (LDP4) 31 15 30 14 0 29 13 28 12 27 11 26 25 24 0 10 9 DP3_4 8
23 7
22 0 6 0
21 5
20 4
0x80000F34 19 18 17 16 DP3_5 3 2 1 0 DP1_5 0x80000F38
23 7
22
21
20 4
19 3
18
17
16 0
6 5 DP2_4
2 1 DP1_4
LCD Dithering Pattern Register (LDP3) 31 30 29 28 27 26 25 24 0 15 14 13 12 11 0 10 9 8
23 7
22 6
21 5 DP2_3
20 4
19 3 0
0x80000F3C 18 17 16 2 1 DP1_3 0
LCD Display Size (LDS) 31 30 29 28 27 15 14 13 12 11
26 10
25 9
24 8
23 7
22 6
21 20 VSIZE 5 HSIZE 4
19 3
0x80000F40 18 17 16 2 1 0
FIELD VSIZE [26:16] HSIZE [10:0]
Description Vertical size: number of active lines Horizontal size: number of active pixels in a line.
Preliminary
14-20
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
0x80000F44
LCD Status Register (LSTATUS) 31 15 30 14 29 13 28 12 27 11 26 10 0 FIELD 25 9 24 0 8 7 6 5 4 3 EF 23 22 21 20 19
18 2 DD
17 1 RU
16 0 FU
Description Even-Field(Read-Only) EF [3] 0: odd field or frame 1: even field or frame Disable Done(Read/Clear). If LEN is disabled, DD will be 1 after current frame has been DD* [2] displayed.. As MDD of LIM register is cleared, it can be LCD interrupt source Register Update(Read/Clear) It indicates that all registers programmed are applied to current frame RU*[1] data. As MRU of LIM register is cleared, it can be LCD interrupt source. FIFO underrun(Read/Clear) It indicates that FIFO underrun has been occurred. In this case, LCLK FU*[0] frequency must be lower. As MFU of LIM register is cleared, it can be LCD interrupt source. For clearing a specified bit, it must be written to 1. If a interrupt is generated, LSTATUS bits, which correspond to the interrupt sources, must be cleared. Otherwise, the uncleared interrupt will be not generated any more. LCD Interrupt Masking Registers (LIM) 31 15 30 14 29 13 28 12 27 11 26 10 25 9 0 FIELD MDD[2] MRU[1] MFU[0] LCD Image Position(LIP) 31 30 29 28 27 15 14 13 12 11 Description Mask "Disable Done Interrupt". Mask "Register Update Interrupt". Mask "FIFO underrun(Read/Clear)". 0x80000F4C 18 17 16 2 1 0 24 0 8 7 6 5 4 3 2 1 0 MDD MRU MFU 23 22 21 20 19 0x80000F48 18 17 16
26 10
25 9
24 8
23 7
22 6
21 20 Y[10:0] 5 4 X[10:0] Description
19 3
FIELD Y [10:0] X [10:0]
Y position to display X position to display
Preliminary
14-21
TCC76x
LCD Image Size(LIS) 31 15 30 14 29 13 28 12 27 11 26 10
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
0x80000F50
25 9
24 8
23 7
22 21 20 HEIGHT[11:0] 6 5 WIDTH[11:0] 4
19 3
18 2
17 1
16 0
FIELD Description HEIGHT [11:0] Image height WIDTH [11:0] Image width If image size is larger than display size, the image is clipped automatically. Therefore, as image base address is changed, the panning operation can be implemented.
Base address
LIS.WIDTH
LIS.HEIGHT
L D S.V SIZ E LDS.HSIZE
LCD Image Base Address0(LIBA0) 31 15 30 14 29 13 28 12 27 11 26 10 25 24 23 22 LIBA0[31:16] 7 6 21 5 20 4 19 3
0x80000F54 18 2 17 1 0 16 0
9 8 LIBA0[15:2]
FIELD LIBA0 [31:2] LCD Image Base Address1(LIBA1) 31 30 29 28 27 26 25 15 14 13 12 11 10
Description Image base address. If a image is YUV format, it is Y base address. 0x80000F5C 18 17 16 2 1 0 0
24 23 22 LIBA1 [31:16] 7 6
21 5
20 4
19 3
9 8 LIBA1 [15:2]
FIELD LIBA1 [31:2]
Description If a image is YUV format, it is U base address. Otherwise, it is not used.
Preliminary
14-22
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
LCD Image Base Address2(LIBA2) 31 15 30 14 29 13 28 12 27 11 26 10 25 24 23 22 LIBA2 [31:16] 7 6 21 5 20 4 19 3
0x80000F60 18 2 17 1 0 16 0
9 8 LIBA2 [15:2]
FIELD LIBA2 [31:2]
Description If a image is YUV data, it is V base address. Otherwise, it is not used.
Preliminary
14-23
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 LCD CONTROLLER
Preliminary
14-24
TCC76x
15 MEMORY CONTROLLER 15.1 Overview
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
The TCC76x has a memory controller for various kind of memory for digital media en-decoding system. It can manipulate SDRAM, Flash (NAND, NOR type), ROM, SRAM type memories, and also support the IDE interface for HDD or USB2.0 device. It has configurable data bus width through the GPIO pin or each configuration register. The data bus width can be configured for each chip select separately The memory controller provide the power saving function for SDRAM (self refresh). The following figure represents the block diagram of memory control unit.
SDCFG
SDRAM State Machine SDRAM Signal Generator
Refresh Controller
AHB
Remap Flag ExtMEM Signal Generator ExtMEM State Machine
Signal Mixer
Memory Control Signals
CSCFGn
Figure 15.1 Memory Controller Block Diagram The registers for memory controller block have the base address of 0xF0000000.
Preliminary
15-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
Table 15.1 Memory Controller Register Map (Base Address = 0xF0000000) Name Address Type Reset Description SDCFG SDFSM MCFG TST CSCFG0 CSCFG1 CSCFG2 CSCFG3 CLKCFG SDCMD 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 R/W R R/W W R/W R/W R/W R/W R/W W 0x62E97010 0xZZZZ_02 0x00000000 0x0B405649 0x0150569A 0x006056BA 0x0A70569A 0xXXXXXX00 SDRAM Configuration Register SDRAM FSM Status Register Miscellaneous Configuration Register Test mode register (must be remained zero) Configuration Register for External Chip Select 0 (nCS0 pin) Configuration Register for External Chip Select 1 (nCS1 pin) Configuration Register for External Chip Select 2 (nCS2 pin) Configuration Register for External Chip Select 3 (nCS3 pin) Memory Controller Clock Count Register SDRAM Command Register
Name
Table 15.2 NAND flash Register Map (Base Address = N * 0x10000000) Address Type Reset Description
NDCMD 0x00 R/W Command Cycle Register NDLADR 0x04 W Linear Address Cycle Register NDRADR 0x08 W Row Address Cycle Register NDIADR 0x0C W Single Address Cycle Register NDDATA 0x10 R/W Data Access Cycle Register *) N represents BASE field of configuration register (CSCFGx ) for each chip select.
Preliminary
15-2
TCC76x
15.2 SDRAM Controller
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
The SDRAM controller supports from 16Mbit up to 512Mbit SDRAM. The SDRAM parameter such as size, refresh period, RAS to CAS delay, refresh to idle delay can be programmed by internal register. Refer to SDRAM cycle diagram in Figure 15.2 SDRAM Configuration Register (SDCFG) 31 30 29 28 27 26 25 24
CL BW CW SDBASE
23 7
22
RC
21 5
20 4
19
RCD
0xF0000000 18 17 16
RD[2:1]
15
RD[0]
14
13
RP
12
11
RW
10
9
8
6
3
AM
2
APD
1
PPD
0
SR
Refresh
*) The reset value means the following configuration. CAS Latency = 2 cycles, CAS Width = 9bit, RAS Width = 12bit, Bus Width = 16bit, SDBASE = 0x20000000 tRC = 7 cycles, tRCD = 2 cycles, tRD = 2 cycles, tRP = 7 cycles, Refresh = (512 + 15) cycles Except for Bit 0 (SR), the sequence below must be followed whenever this register is written. 1. 2. 3. Clear SDEN bit of MCFG register (SDRAM controller is disabled) Update SDCFG register value Set SDEN bit of MCFG register (SDRAM controller is enabled and MRS cycle is issued to the SDRAM).
Although the reset value of SDEN bit is "0", the boot ROM enables the SDEN bit in JTAG debug mode,. Thus, do not rely on the default value of SDEN bit. Always follow the sequence above if JTAG debugging is required.
CL [31] 0 1
CAS Latency (tCL) CAS latency is 2 cycle CAS latency is 3 cycle
*) Do not change this bit when SDEN bit of MCFG register is "1". Disable SDEN first. After this bit is written, SDEN bit must be re-enabled for SDRAM MRS cycle.
BW [30] 0 1 CW [29:28] 0, 1 2 3
Bus Width Select Bus width for SDRAM is 32 bit (valid only in TCC761) Bus width for SDRAM is 16 bit CAS Width 8 bit is used for CAS address 9 bit is used for CAS address 10 bit is used for CAS address
*) 16Mbit : CAS = 8 bit, RAS = 11 bit 64Mbit : CAS = 8 bit, RAS = 12 bit 128Mbit : CAS = 9 bit, RAS = 12 bit 256Mbit : CAS = 9 bit, RAS = 13 bit 512Mbit : CAS =10bit, RAS = 13 bit
SDBASE
[27:24]
SDRAM Base Address Indicates the MSB 4bit of SDRAM area. That is SDRAM base = 0xN0000000
N
Preliminary
15-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
RC [23:21] n RCD [20:18] n RD [17:15] n RP [14:12] n RW [11:10] {x,1} {0,0} {1,0}
Delay of Refresh to Idle (tRC) n number of HCLK cycle is used to meet the refresh to idle delay time Delay of RAS to CAS (tRCD) (n+1) number of HCLK cycle is used to meet the RAS to CAS delay time Delay of Read to Precharge (tRD) n number of HCLK cycle is used to meet the read to precharge time Delay of Precharge to Refresh (tRP) (n+1) number of HCLK cycle is used to meet the precharge to refresh time RAS Width 11bit is used for RAS address bus 12bit is used for RAS address bus 13bit is used for RAS address bus
*) 16Mbit : CAS = 8 bit, RAS = 11 bit 64Mbit : CAS = 8 bit, RAS = 12 bit 128Mbit : CAS = 9 bit, RAS = 12 bit 256Mbit : CAS = 9 bit, RAS = 13 bit 512Mbit : CAS =10bit, RAS = 13 bit
Refresh [9:4] n AM 0 1 APD 0 PPD 0 1
Refresh Cycle Every (n * 512 + 15) number of HCLK cycle has passed, the SDRAM refresh request is generated. If on going cycle has finished, the refresh cycle starts. Real refresh period depends on the period of HCLK. Address Matching Configuration Bit BA-RAS-CAS RAS-BA-CAS Reserved Reserved for ChipTest. Must be written as "0" Precharge Power-Down Mode Disable precharge power-down mode Enable precharge power-down mode When sdram in precharge-idle state, CKE signal would be zero for powerdown. In this case, the redundant 1 cycle is needed to enter the active state. Self-Refresh Mode Exit from the self-refresh mode Enter the self-refresh mode 0xF0000004 18 17 16 2 1 0
SR 0 1
SDRAM FSM Status Register (SDFSM) 31 30 29 28 27 26 25 15 14
0
24
0
23 7
22 6
21 5
20 4
19 3
13
12
11
10
9
8
SDFSM
This register is read only and represents current status of finite state machine in the SDRAM controller. This can be used for test purpose only.
Preliminary
15-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
SDRAM Write Cycle (Non-sequential) SDCLK SDnCS nRAS nCAS XA nWE DQ DQM RAS Cmd DQ0 DQM0 WR Cmd DQ1 DQM1 WR Cmd Stop Cmd RAS tRCD CAS0 CAS1
SDRAM Read Cycle (Row Actived) SDCLK SDnCS nRAS nCAS nWE DQ DQM RD Cmd SDRAM Precharge / Refresh Cycle SDCLK SDnCS nRAS nCAS nWE DQ Valid PreC Cmd RFR Cmd SDRAM controller goes to IDLE state tRD tRP tRC tCL DQ0 tCL Stop Cmd DQ2 DQ3
Figure 15.2 SDRAM Cycle Diagram
Preliminary
15-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
15.3 Miscellaneous Configuration
In this register, there are various special flags for the TCC76x system. One of them is for supporting boot PROM. At initialization, the lower address space (0x00000000 ~ 0x0FFFFFFF) is mapped to internal or external boot ROM. But after initialization, these space must be mapped to a RAM as the system program including interrupt vector table is located in this area. To satisfy this requirement, the TCC76x provide RM(Remap) flag. BM flag is used to select one of the boot procedures. Refer to Section "BOOTING PROCEDURE" for details. BM flag contains the state of GPIO_B[24,22,21] pins at the rising edge of the nRESET pin. BW flag is used to detect the initial system bus width configuration. This flag is read-only, and contains the state of GPIO_A[9:8] pin at the rising edge of nRESET pin. So user can control the bus width by pulling up or down the GPIO_A[9:8] pin.
Miscellaneous Configuration Register (MCFG) 31 30 29 28 27 26 25 24 23
XXXX
22 6
SDT
21 5
20 4
19 3
SDS
0xF0000008 18 17 16 2
SRF
15
RDY
14
XDM
13
X
12
11
BW
10
9
BM
8
7
SDW
1
GPO
0
RM
JTEN SDEN
RDY [15] Type Bus Ready Flag 0 Represent that READY pin is low. R 1 Represent that READY pin is high. *) This flag reflects READY pin's state. READY pin is used to extend the access cycle for the external memories. It can control directly the cycle of external memory access by setting the URDY bit of each configuration register and also can be used as a ready flag by polling the state of this bit, especially for NAND flash interfacing. XDM [14] 0 1 BW [12:11] 00, 01 Type R/W Type Data-Bus Output Mode In idle state, the data bus would be in input-mode. (Default) In idle state, the data bus would be in output mode.
Bus Width Flag The corresponding memory is configured by 32bit data bus. The 32bit bus width is valid only in TCC761. R 10 The corresponding memory is configured by 16bit data bus. 11 The corresponding memory is configured by 8bit data bus. BW is the status of GPIO_A[9:8] at the rising edge of nRESET signal. The bus-width of memory attached at nCSx register is determined as follows. BW (of CSCFGx) = BW (of MCFG) ^ BW (that user want) BM [10:8] n Type R Boot Mode The state of GPIO_B[24,22,21] pins at reset. Refer to Chapter "BOOTING PROCEDURE" for boot mode.
Preliminary
15-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
SDW [7] 0 1 SDT [6] 0 1 JTEN [5] 0 1
Type R/W Type R/W Type R/W
SDRAM High-Frequency Wait No additive wait cycle Additive wait cycle Type of SDRAM Single-Data-Rate SDRAM Double-Data-Rate SDRAM JTAG Enable JTAG port is disabled JTAG port is enabled
SDEN [4] Type SDRAM Controller Enable 0 SDRAM controller is disabled R/W 1 SDRAM controller is enabled *) When this bit goes from low to high, SDRAM MRS cycle is generated. This bit must be cleared before CL bit of SDCFG register is changed. SDS [3] 0 1 SRF [2] Type R/W Type SD_CLK output select SDRAM Clock is out from SD_CLK pin GPO bit is out from SD_CLK pin
Self Refresh Cycle Generation If SDRAM is in standby mode, the refresh cycle is generated a 0 few times automatically, and SDRAM exits from standby state and goes back into idle state. R/W If SDRAM is not in standby mode, the self-refresh cycle is 1 generated, and the SDRAM enters into standby mode and stay this mode until this flag goes back to low. *) Do not set while program is executing in SDRAM. SR bit of SDCFG register has the same function.. Either one can be used for self-refresh mode control. It is recommended to use the following example sequence to control self-refresh mode. To enable self-refresh mode, 1. 2. 3. Manipulate cache coherency if necessary. Set SR bit of SDCFG register Set SDS bit of MCFG register
To exit from self-refresh mode, 1. 2. Clear SDS bit of MCFG register Clear SR bit of SDCFG register
The above sequences must be executed in the non-SDRAM area, like internal SRAM or NOR flash and while the SDRAM is in self-refresh mode, code should not access the SDRAM area. GPO [1] 0/1 Type R/W SD_CLK output When SDS bit is high, this bit is out through SD_CLK pin
Preliminary
15-7
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
RM [0] 0 1
Type R/W
Remap Flag The area 0 (0x00000000 ~ 0x0FFFFFFF) space is mapped to internal / external boot ROM The area 0 space is released from boot ROM
In initialization, RM flag direct that the lower address space is mapped to internal or external boot ROM. The boot program in internal or external ROM set RM flag high after going to address space that is not in lower address space(0x00000000~0x0FFFFFFF). After RM flag is set to 1, the lower address space is released from internal or external boot ROM, so the lower address space can be mapped to other memories including SDRAM or internal SRAM by changing the base address of that memories. The RM flag can be restored to 0 by user request, but because the lower address space is remapped to boot ROM again, care must be taken not to illegally change the RM flag.
Preliminary
15-8
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
15.4 External Memory Controller
External memory controller can control external memories such as NAND or NOR type flash memory and ROM, SRAM type memory. These memories are selected by nCS3 ~ nCS0 pins. The cycle parameter for accessing external memory can be configured by internal registers. In case of NAND flash, additional parameters for address, command and data cycles can be provided. External Chip Select n Configuration Register (CSCFGx) 31 30 29 28 27 26 25 24 23 22 21
OD WD PW[7:6] BW MTYPE CSBASE
20 4
0xF0000010 + (x * 4) 19 18 17 16
URDY
RDY
PW[5:4]
15
14
13
12
11
10
CADR
9
8
7
STP
6
5
3
2
1
HLD
0
PW[3] AMSK
PSIZE
PW[2:0]
*) The reset value of each CSCFGx register means the following configuration for each chip select. Chip Select 0 : 16bit, SRAM, Base = 0x40000000, tSTP=1, tPW=2, tHLD=1 Chip Select 1 : 32bit, IDE, Base = 0x50000000, not use Ready, tSTP=2, tPW=4, tHLD=2 Chip Select 2 : 32bit, NAND, Base = 0x60000000, AMSK=1, PSIZE=1, CADR=3, tSTP=2, tPW=8, tHLD=2 Chip Select 3 : 16bit, NOR, Base = 0x70000000, tSTP=2, tPW=4, tHLD=2
OD 0 1 WD 0 1
Delayed `OE' Signal Normal STP and HLD timing would be applied. When STP and HLD are zero, 1 cycle would be added for delayed by half-pulse for OE signal Delayed `WE' Signal Normal STP and HLD timing would be applied. When STP and HLD are zero, 1 cycle would be added for delayed by half-pulse for WE signal
*bw [27:26] Bus Width Select 0, 1 Bus width = 32 bit (valid only in TCC761) 2 Bus width = 16 bit 3 Bus width = 8 bit *) bw is calculated by xoring the BW field of MCFG register and BW field of CSCFGx register, that is bw = BW(of MCFG) ^ BW(of CSCFGx). BW(of MCFG) is acquired by the status of GPIO_A[9:8] at the rising edge of nRESET signal. So, if user want to set bus-width independently to the BW of MCFG, you must set the BW of CSCFGx as like as the follows. BW (of CSCFGx) = BW (of MCFG) ^ BW (that user want) MTYPE [25:24] 0 1 2 3 Type of External Memory NAND type IDE type SMEM_0 type (Ex : ROM, NOR flash) Byte write control signal (DQM) is not needed. SMEM_1 type (Ex : SRAM) Byte write control signal (DQM) is needed.
CSBASE [23:20] Chip Select n Base Address M Indicates the MSB 4bit of nCS[n] area. The base address of nCS[n] is set to M * 0x10000000.
Preliminary
15-9
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
Use Ready Ready / Busy signal monitoring is enabled 1 The memory controller extends access cycle until the state of READY pin indicates that the access request has accomplished. *) Refer to Figure 15.3 for ready(busy) cycle extension. Don't use this feature when access NAND flash. NAND flash's READY signal is for waiting from end of command cycle to start of data cycle so it is not adequate for extension of each cycle. Ready / Busy Select The READY(MODE0) pin indicate the READY signal. 0 The memory controller extends access cycle until this pin goes to high state. The READY(MODE0) pin indicate the BUSY signal. 1 The memory controller extends access cycle until this pin goes to low state. *) Refer to Figure 15.3 for ready/busy cycle extension. AMSK [14] Address Mask Bit 0 Upper half of data bus is masked to zero. *) In case of 16bit width NAND flash, the upper half byte must be held low, during address cycles. This bit must be set to zero. But if the system uses multiple NAND flashes by sharing a chip select but separating each data to 16 or 32bit data bus of the TCC76x, the AMSK must be set to 1, so the address can be fed to each NAND flashes. Page size of NAND Flash The size of one page for NAND type flash. psize It represents byte per page calculated by the following equation. 1 Page = 256 * 2psize *) Refer to Table 15.3 about the relationship between the address generation and each page size configuration. Number of Address Cycles The number of address command cycle for NAND type flash. N (N+1) cycle is used for generating address cycle command. *) Refer to sub-register of NAND type memory for more information of PSIZE and CADR field. STP [8:6] N
PW[7:0]
[29:28,17:15,5:3]
URDY [19]
RDY [18]
PSIZE [13:12]
CADR [11:9]
Number of Cycle for Setup Time (tSH) N cycle is issued between the falling edge of nCS[n] and nOE / nWE. Number of Cycle for Pulse Width (tPW) (N+1) cycle is issued between the falling and rising edge of nOE / nWE. Number of Cycle for Hold Time (tHLD) N cycle is issued between the rising edge of nOE / nWE and nCS[n].
N ( = 0~255 ) HLD [2:0] N
The following figure displays the element cycle diagram for external memories.
Preliminary
15-10
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
SMEM_0 Type Cycle (Bus width >= Data width, URDY=0) nCS XA nOE nWE DQ DQR ADDR0 tPW tSH tHLD tSH tPW DQW tHLD ADDR1
SMEM_0 Type Cycle (Bus width < Data width, URDY=1, RDY=0) tPW + tWait = tPW 1 + tPW 2 + tWait ADDR0 tPW 1 tSH tWait READY DQ DQRL DQRH tPW 2 tHLD tSH1 tSH2 tWait tSH + tWait = tSH1 + tSH2 + tWait ADDR1 tPW tHLD
nCS XA nOE
SMEM_1 Type Cycle (Bus width >= Data width, URDY=0) nCS XA nOE nWE DQM1 DQM0 DQ[15:8] DQ[7:0] DQ0 DQ1 ADDR0 tPW tSH tHLD tSH tPW tHLD ADDR1
Figure 15.3 Basic Timing Diagram for External Memories
In case of IDE type memories, there are two chip-enable signals for it. In the TCC76x, each enable signal can be controlled by offset address space. `nCS0' reflects that the offset address range of 0 ~ 0x1F is accessed, `nCS1' reflects that 0x20 ~ 0x3F is accessed. For larger address than 0x3F, if bit5 of address value means which enable signal is activated. (0 to `nCS0', 1 to `nCS1')
Preliminary
15-11
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
Memory Controller Clock Count Register (CLKCFG) 31 30 29 28 27 26 25 24 23 22 21
Reserved
20 4
19 3
0xF0000020 18 17 16 2 1
CNT[2:0]
15
14
13
12
11
10
9
Reserved
8
7
6
5
0
CNT [2:0]
N
Count Select for Clock Gating The internal clock of the Memory Controller can be gated to save power. These bits selects the clock gating ratio. The timing parameters of CSCFGx registers should be re-written with appropriate values. These bits also affect the SD_CLK output. Do not enable this feature when DDR SDRAM is used. SEL[2:0] SD_CLK and Internal Clock 1 HCLK / 2 2 HCLK / 4 3 HCLK / 6
SDRAM Command Register (SDCMD) 31 30 29 28 27 26 25 24
Reserved
23 7
22 6
21 5
20 4
19 3
0xF0000024 18 17 16
A10
15
nCS
14
13
12
nWE
11
10
9
8
2
1
0
nRAS nCAS
BA[1:0]
A[9:0]
When this register is written, corresponding SDRAM signal is output to the SDRAM. This is a write only register and read data is undefined. Any value written to this register must be a valid SDRAM command (MRS or EMRS, etc).
Preliminary
15-12
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
Sub-registers of NAND type memory
In case of NAND flash type memories, there are several sub-registers for generating command, address, and data cycles. Followings are these sub-registers. (M is base field of CSCFGx register) Except the data register (NDDATA), the sub-register has implicit size of 32bit, so the bus-width of CSCFGx register does not affect the cycle of command and address registers. It only affects the cycle of data register. Command Cycle Register (NDCMD) 31 30 29 28 27 26 25
NDCMD3
24 8
23 7
22 6
21 5
20 4
19 3
0x10000000 * M 18 17 16 2 1 0
NDCMD2
15
14
13
12
11
10
9
NDCMD1
NDCMD0
*) If bus width of NAND flash is more than 8bit, the NDCMD1 ~ 3 may be used as command register, otherwise only NDCMD0 is used as command register. The following values are an example commands for NAND flash of SAMSUNG. Refer to corresponding datasheet of NAND flash chip for more detailed list of command s. 0x00/0x01 : Page Read Command 0x80 : Page Program Command 0x60 : Block Erase Command 0x70 : Status Read Command
(generated by reading from 0xM0000700 address)
Linear Address Cycle Register (NDLADR) 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8
23 7
22 6
21 5
0x10000000 * M + 0x04 20 19 18 17 16 4 3 2 1 0
NDLADR[31:16] NDLADR[15:0]
*) By writing to this register, memory controller generates linear address cycle for NAND flash. Row Address Cycle Register (NDRADR) 31 30 29 28 27 26 25 24 15 14 13 12 11 10 9 8 0x10000000 * M + 0x08 20 19 18 17 16 4 3 2 1 0
23 7
22 6
21 5
NDRADR[31:16] NDRADR[15:0]
*) By writing to this register, memory controller generates row address cycle for NAND flash. Table 15.3 represents the relation between each cycle and address generation. User must set this information appropriately to PSIZE and CADR field of CSCFGx register ahead of accessing NAND data.
Preliminary
15-13
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 MEMORY CONTROLLER
Table 15.3 Page size of NAND Flash # of Cycle 1 2
st
Address Generation PSIZE = 0 ADR[7:0] ADR[15:8] ADR[23:16] ADR[31:24] PSIZE = 1 ADR[7:0] ADR[16:9] ADR[24:17] ADR[31:25] PSIZE = 2 ADR[7:0] ADR[10:8] ADR[18:11] ADR[26:19] PSIZE = 3 ADR[7:0] ADR[11:8] ADR[19:12] ADR[27:20]
nd
3rd 4th
th
5 ADR[31:27] ADR[31:28] *) ADR means address value that is written to NDLADR or NDRADR register. The shaded cycles represent row address cycles. That is, NAND address cycles start from there when NDRADR register is accessed. Single Address Cycle Register (NDIADR) 31 30 29 28 27 26 25 24 23
Reserved
22 6
21 5
0x10000000 * M + 0x0C 20 19 18 17 16 4 3 2 1 0
15
14
13
12
11
10
9
8
7
Reserved
NDIADR
*) When CPU writes to this register, one cycle of address cycle is generated. Data Register (NDDATA) 31 30 29 28 27
NDDATA3
26 10
25 9
24 8
23 7
22 6
21 5
0x10000000 * M + 0x10 20 19 18 17 16
NDDATA2
15
14
13
12
11
4
3
2
1
0
NDDATA1
NDDATA0
*) NDDATA3~1 may be used as the value of data register, otherwise only NDDATA0 is used as data register. It is dependant on the bus-width of CSCFGx register of NAND flash.
15.5 Internal Memory
In the TCC76x, there is 64Kbytes of SRAM for general purposes and 4Kbytes of ROM for system initialization. SRAM area is dedicated to area 3 (0x30000000 ~ 0x3FFFFFFF), and also accessed by area 0 (0x00000000 ~ 0x0FFFFFFF) when there are no devices assigned to area 0. ROM area is dedicated to area E (0xE0000000 ~ 0xEFFFFFFF), and also accessed by area 0 (0x00000000 ~ 0x0FFFFFFF) when RM flag of MCFG register is cleared to 0. In case of internal ROM, access cycle can be extended by inserting 1 wait cycle. This wait cycle is determined by writing any value to ROM area. When writing to address of which the bit 2 is 1 (such as 0xE0000004, 0xE000000C, 0xE0000014, ...) , the wait cycle is to be inserted from the next ROM access cycle. On the other hand writing to address of which the bit 2 is 0 (such as 0xE0000000, 0xE0000008, 0xE0000010, ...), the wait cycle is to be removed from the next ROM access cycle. In the TCC76x, zero wait access is guaranteed for the internal ROM and SRAM up to 100MHz AHB clock. The wait cycle insertion feature was preserved for the TCC72x. There is no need to enable wait cycle.
Preliminary
15-14
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ECC (ERROR CORRECTION CODE)
16 ECC (Error Correction Code) 16.1 Functional Description
The ECC (Error Correction Code) is used to correct data error in storage device or various kind of communicating system. The TCC76x has a simple ECC generation module that calculate these ECC for this purpose. By enable ECC module, it consistently monitors internal bus activity and calculate ECC whenever there is read or write cycle from/to a predefined memory area. The area can be determined by special register so this module can be used ECC calculation itself not only for specific storage device such as NAND flash. The following figure represents block diagram including internal bus connection for ECC module.
ECC Control Register ECC in/output Register Base Address Address Mask AHB
ECC Core
HCLK HREADY HRDATA HWDATA HTRANS HADDR HSIZE Memory Controller External Storage Device
Figure 16.1 ECC Block Diagram
Preliminary
APB
16-1
TCC76x
16.2 Register Description
Name ECC_CTRL ECC_BASE ECC_MASK ECC_CLR SLC_ECC0 SLC_ECC1 SLC_ECC2 SLC_ECC3 SLC_ECC4 SLC_ECC5 SLC_ECC6 SLC_ECC7 MLC_ECC0W MLC_ECC1W MLC_ECC0R MLC_ECC1R
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ECC (ERROR CORRECTION CODE)
Table 16.1 Address Type 0x00 R/W 0x04 R/W 0x08 R/W 0x0C W 0x10 R 0x14 R 0x18 R 0x1C R 0x20 R 0x24 R 0x28 R 0x2C R 0x40 W 0x44 W 0x48 R/W 0x4C R/W
ECC Register Map (Base Address = 0x80000900) Reset Description 0x00000000 ECC Control Register 0x00000000 Base Address for ECC Calculation 0x00000000 Address mask for ECC area. Clear ECC output register 0x00000000 1st Block ECC output for SLC NAND 0x00000000 2nd Block ECC output for SLC NAND 0x00000000 3rd Block ECC output for SLC NAND 0x00000000 4th Block ECC output for SLC NAND 0x00000000 5th Block ECC output for SLC NAND 0x00000000 6th Block ECC output for SLC NAND 0x00000000 7th Block ECC output for SLC NAND 0x00000000 8th Block ECC output for SLC NAND MLC NAND ECC calculation register 0 MLC NAND ECC calculation register 1 0x00000000 Calculated ECC output 0 for MLC NAND 0x00000000 Calculated ECC output 1 for MLC NAND
ECC Control Register (ECC_CTRL) 31 30 29 28 27 26 25 24 0 15 14 13 12 11 10 9 8 ECC_CNT[3:0] MLC_STAT[3:0] ECC_CNT [20:12] N MLC_STAT 1000 0100 0010 0001 HLD 1 EC0 1 ME 1 0
[4] [5] [11:8]
23 7 HLD
22 6 0
21 5 EC0
20 4 ME
0x80000900 19 18 17 16 ECC_CNT[8:4] 3 2 1 0 SLC_CNT[2:0] SE
ECC Word Counter Means that N number of words are calculated Represent Internal State for MLC ST_ECC : Compare state. It compares two ECC for error-checking. ST_WR : Write state. It calculates ECC for write cycle. ST_RD : Read state. It calculates ECC for read cycle. ST_IDLE : Idle state. It waits until there is access for MLC device. ECC Hold Hold Enabled. ECC output register is not changed. ECC Zero Means that ECC output register (MLC_ECC0R & MLC_ECC1R for MLC, SLC_ECC0 & SLC_ECC1 for SLC) contains 0. MLC ECC Enable Enable ECC for MLC Disable ECC of MLC
[7]
Preliminary
16-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ECC (ERROR CORRECTION CODE)
SLC_CNT N (0 ~ 7)
[3:1]
ECC Block Count Means that N number of ECC block (256 bytes) are calculated. This is useful to determine how many ECC output registers are valid. That is, N number of ECC output register counting from SLC_ECC0 are valid. SLC ECC Enable Enable ECC for SLC Disable ECC of SLC 0x80000904 18 17 16 2 1 0
SE 1 0
[0]
ECC Base Address Register (ECC_BASE) 31 30 29 28 27 26 25 24 23 22 ECC_BASE[31:16] 15 14 13 12 11 10 9 8 7 6 ECC_BASE[15:0] ECC Address Mask Register (ECC_MASK) 31 30 29 28 27 26 25 24 0 15 14 0 13 12 11 10 9 8
21 5
20 4
19 3
23
22
21
20
19
0x80000908 18 17 16
7 6 5 4 3 2 1 0 ECC_MASK[9:0] 0 The ECC is calculated whenever the specified region of memory is accessed. The region for ECC calculating is determined by ECC_BASE & ECC_MASK register. The real base address is determined by following formula. Real base address = ECC_BASE(0x80000904) & ~(ECC_MASK[9:0] << 2) (The real base address is assumed to be word aligned, so the least 2 bits are always 0.) The size of region is also determined by ECC_MASK register. If ECC_MASK register have N concatenated 0 from LSB, the region size is set to 2N bytes.
ECC Clear Register (ECC_CLR) 31 30 29 28 27 26 15 14 13
24 23 22 21 20 19 Don't care 12 11 10 9 8 7 6 5 4 3 2 1 0 Don't care Whenever this register is written by any value, all ECC output registers are cleared to 0.
25
0x8000090C 18 17 16
ECC Output Register for SLC (SLC_ECCx) 0x80000910 + x*4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 SLC_ECCx_0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLC_ECCx_1 SLC_ECCx_2 These registers contain ECC output for SLC. It calculates ECC of SSFDC standard, and can contain up to 8 block of data. Every time it finishes calculating ECC for each block, it shifts the ECC values for previous block from SLC_ECC0 upward to SLC_ECC7 register. So the ECC for last block is always stored at SLC_ECC0 register. For each output register, there are a total of 22 bits of parity data (6 bits for column parity Preliminary 16-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ECC (ERROR CORRECTION CODE)
and 16 bits for line parity) as follows: P1, P1', P2, P2', P4, P4', P8, P8', P16, P16', ......, P1024, P1024' The parity data that have been generated are stored as follows. SLC_ECCx_0 SLC_ECCx_1 SLC_ECCx_2 Bit7 P64 P1024 P4 Bit6 P64' P1024' P4' Bit5 P32 P512 P2 Bit4 P32' P512' P2' Bit3 P16 P256 P1 Bit2 P16' P256' P1' Bit1 P8 P128 1 Bit0 P8' P128' 1
ECC Evaluation Register for MLC (MLC_ECC0W) 31 30 29 28 27 26 25 24 23 22 MLC_ECC0W[31:16] 15 14 13 12 11 10 9 8 7 6 MLC_ECC0W[15:0]
21 5
20 4
19 3
0x80000940 18 17 16 2 1 0
ECC Evaluation Register for MLC (MLC_ECC1W) 0x80000944 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 MLC_ECC1W[30:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MLC_ECC1W[15:0] To evaluate ECC for MLC, write acquired ECC to these registers. The MLC_ECC0W is LSB word and MLC_ECC1W is MSB. The order of writing should be LSB first and then MSB. After writing to MLC_ECC1W, ECC module starts evaluation and its state can be monitored by checking MLC_STAT field of ECC_CTRL register. After finishing evaluation, user can determine whether ECC error occurred or not by checking EC0 flag of ECC_CTRL register or checking MLC_ECC0R & MLC_ECC1R registers. ECC Output Register for MLC (MLC_ECC0R) 31 30 29 28 27 26 25 24 23 22 MLC_ECC0R[31:16] 15 14 13 12 11 10 9 8 7 6 MLC_ECC0R[15:0] 0x80000948 18 17 16 2 1 0
21 5
20 4
19 3
ECC Output Register for MLC (MLC_ECC1R) 0x8000094C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 MLC_ECC1R[30:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MLC_ECC1R[15:0] If there are ECC error, the EC0 flag of ECC_CTRL register is set to 1. By reading MLC_ERR1R & MLC_ERR0R register and using appropriate algorithm, user can fix maximum 3 symbols of error.
Preliminary
16-4
TCC76x
17 I2C CONTROLLER
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 I2C CONTROLLER
17.1 Functional Description
I2CCLK from Clock Controller
Prescale Register
Clock Generator
Command Register
Byte Command Controller Bit Command Controller
SCL
APB
Status Register
SDA
Transmit Register
DataI/O Shift Register
Receive Register
Figure 17.1 I2C Block Diagram
17.2 Related Blocks
Before enable the I2C Controller, CFGI2C[1:0] of MISCFG register (0x80000A1C) must be set according to the external connection. CFGI2C[1:0] enables I2C signals on to the GPIO pins as listed in the table below. CFGI2C has a priority over GPIO control bits. Note that GPIO_D[17:16] is also shared with CIF (Camera Interface) signals. When CIFEN is set, GPIO_D[17:16] will be assigned to CIF signals regardless of CFGI2C value. Table 17.1 I2C Signal Mapping CFGI2C[1:0] SCL SDA 00 Disabled Disabled 01 GPIO_A[9] GPIO_A[8] 10 GPIO_A[11] GPIO_A[10] 11 GPIO_D[17] GPIO_D[16] 11 Disabled Disabled
CIFEN X X X 0 1
At power on reset, CFGI2C is disabled and the I2C signals are treated as normal GPIO. GPIO_A[9:8] are used as Bus Width Configuration bits (BW[1:0]) at power on reset. Due to this functionality, I2C signals may not be selected. Refer to section "MEMORY CONTROLLER" for BW[1:0] description. (MCFG register) Preliminary 17-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 I2C CONTROLLER
After the signals are enabled, I2CCLK (the main clock of I2C) must be enabled and configured to the proper frequency. Refer to section "CLOCK GENERATOR" for I2CCLK (EX2CLK) related descriptions.
For internal synchronization, the APB clock frequency must be faster than the I2CCLK frequency. fI2CLK fHCLK / 4.0
17.3 Register Description
Name PRES CTRL TXR CMD RXR SR Address 0x00 0x04 0x08 0x0C 0x10 0x14 Table 17.2 I2C Register Map (Base Address = 0x80000800) Type Reset Description R/W 0xFFFF Clock Prescale register R/W 0x0000 Control Register W 0x0000 Transmit Register W 0x0000 Command Register R 0x0000 Receive Register R 0x0000 Status Register 0x80000800 18 17 16
Prescale Register (PRES) 31 30 29 28 27 26 15 14 13 12 11 10
25 9
24 0
23
22
21
20
19
8 7 6 5 4 3 2 1 0 Clock Prescale data This register is used to prescale the SCL clock line. Due to the structure of the I2C interface, the core uses a 5*SCL clock internally. The prescale register must be programmed to this 5*SCL frequency (minus 1). Change the value of the prescale register only when `EN' bit is cleared. Example : CLK Input frequency = 8MHz , Desired SCL frequency = 100KHz Prescale = ( 8MHz / (5*100KHz) ) - 1 = 15 Control Register (CTR) 31 30 29 28 27 15 14 13 12 0 EN [7] 0 1 IEN [6] 0 1 MOD 0 1
[5]
26 10
25 9
24 0 8
23 7 EN
22
21
20 4
19 3
0x80000804 18 17 16 0
11
6 5 IEN MOD
2 1 RESERVED
I2C Core enable bit Disabled Enabled I2C Core interrupt enable bit Disabled Enabled I2C Data Width 8bit Mode 16bit Mode
Preliminary
17-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 I2C CONTROLLER
Transmit Register (TXR) 31 30 29 28 27 26 15 14 13 12 11 10
25 9
24 0
23
22
21
20
19
0x80000808 18 17 16
8 7 6 5 4 3 2 1 0 Transmit Data When CTRL[5] is set, in case of 16Bit Mode is selected, Transmit Data bit width become 16 bit. Default mode is 8bit mode. Command Register (CMD) 31 30 29 28 27 26 15 14 13 12 0 STA [7] 0 1 STO 0 1
[6]
25 9
24 0 8
23 7 STA
22 6 STO
21 5 RD
20 4 WR
19 3 ACK
0x8000080C 18 17 16 2 1 0 RESERVE IACK
11
10
Start Condition Generation Disabled Enabled Stop Condition Generation. Disabled Enabled Read From Slave Disabled Enabled Write to Slave Disabled Enabled Sent ACK Enabled Disabled Interrupt Acknowledge Clear a pending interrupt 0x80000810 18 17 16
RD [5] 0 1 WR [4] 0 1 ACK 0 1 IACK 0 1 Receive Register (RXR) 31 30 29 28 27 15 14 13 12 11
[3]
[0]
26 10
25 9
24 0
23
22
21
20
19
8 7 6 5 4 3 2 1 0 Receive Data When CTRL[5] is set, in case of 16Bit Mode is selected, Receive Data bit width become 16 bit. Default mode is 8bit mode.
Preliminary
17-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 I2C CONTROLLER
Status Register (SR) 31 30 29 28 27 15 14 13 12 0 11
26 10
25 9
24 0 8
23 7
22 6
21 5
AL
20 4
19 3
0x80000814 18 17 16 2 1
TIP
0
IF
RxACK BUSY
RxACK 0 1 BUSY 0 1
[7]
Received acknowledge from slave No Acknowledge received Acknowledge received I2C Bus Busy `0' after STOP signal detected `1' after START signal detected Arbitration lost The core don't lost arbitration The core lost arbitration a STOP signal is detected, but non requested the master drives SDA high, but SDA is low
[6]
AL[5] 0 1 Arbitration is lost when :
TIP [1] 0 1 IF
[0]
Transfer in progress Transferring Data Transfer Complete Interrupt Flag Interrupt is pending
0 1
Preliminary
17-4
TCC76x
18 CAMERA INTERFACE 18.1 Overview
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CAMERA INTERFACE
The TCC76x provides Camera Interface (CIF). The features of CIF are Various formats timings are supported. CCIR 601/656 4:4:4, 4:2:2, 4:2:0 YCbCr(YUV/RGB) Bayer RGB, 555RGB, 565RGB (16/8 bits bus) Data Packing from each channel data DMA transfer with programmable burst count (1, 2, 4, 8 bursts) 32 depths, 32 bits FIFO The following parameters can be programmed. The input format of image The horizontal and vertical size of image The packing method of the each channel data The following figure shows the block diagram of Camera Interface.
Camera Interface
cmosif_ macro Y_FIFO
Data[7:0] HS
cmosif_ onoff
cmosif_ separator
cmosif_ dispatcher
U_FIFO V_FIFO
cmosif_ dma AHB BUS APB BUS
VS
CAM CLK
Iclk Hclk Pclk
cmosif_ clkctrl
cmosif_ reg
Camera Interface CAMCLK (out) pi_ICLK (in) INTCLK / CAMCLK (GPIO_D[15], bidir)
ICLK
cmosif_ clkctrl
INTCLK
CLK_ CTRL
Figure 18.1 CIF Block Diagram The input data can be optionally separated into three color components. Each channel composes of 8 bits and can be packed up to 32 bits. The packing sequence starts from LSB and the results are stored to the FIFOs. The data stored in the FIFOs are transferred to memory by its own DMA master controller. 1, 2, 4 and 8 burst transfer are supported by DMA master.
Preliminary
18-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CAMERA INTERFACE
Figure 18.2 shows the packing method.
pixel clock HS Y[7:0] CbCr[7:0]
MSB
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Cb6 Cr6 Cb8 Cr8
LSB MSB LSB
Y3
Y2
Y1
Y0
Y1 Y5
31
Cr0 Y0 Cb0 Y2 Cb2 Y4 Cb4
0
Cb6 Cb4 Cb2 Cb0 Cr6 Cr4 Cr2 Cr0
31 0
Y3 Cr2 Cr4
Packing at separating each channel
Unpacking at separating each channel
Figure 18.2 Packing Method
The CIF asserts interrupt signal after each frame image has been stored to memory.
18.2 Related Blocks
To enable CIF (Camera Interface), CIFEN bit of MISCFG register (0x80000A1C) must be set to "1". CIFEN bit enables Camera Interface signals on to the GPIO pins listed in the table below. CIFEN has a precedence over GPIO control bits. Table 18.1 CIF Signal Mapping Camera Interface Signals GPIO Pins HS GPIO_D[17] VS GPIO_D[16] CAMCLK GPIO_D[15] Data[7:4] GPIO_D[21:18] Data[3:0] GPIO_A[3:0] At power on reset, CIFEN is disabled and the CIF signals are treated as normal GPIO. After the signals are enabled, CIFCLK (the main clock of CIF) must be enabled and configured to the proper frequency. Refer to section "CLOCK GENERATOR" for CIFCLK related descriptions.
Preliminary
18-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CAMERA INTERFACE
4:4:4 format
CLK HS Y[7:0] CbCr[7:0] Y0 Y1 Y2 Y3 Y4 Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4
pixel clk * 2 * YCbCr, YUV, RGB [Y(G), Cb(U,R), Cr(V,B)]
4:2:2 16bits format (CCIR-601)
CLK HS Y[7:0] CbCr[7:0] Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Cb6 Cr6 Cb8 Cr8
pixel clock * YCbCr, YUV, RGB [Y(G), Cb(U,R), Cr(V,B)]
4:2:2 8bits format (CCIR-656)
CLK HS YCbCr[7:0] Cb0 Y0
pixel clock * 2 * YCbCr, YUV, RGB [Y(G), Cb(U,R), Cr(V,B)]
Cr0 Y1 Cb2 Y2
Cr2 Y3 Cb4 Y5
4:2:0 16, 12bits format
CLK HS Y[7:0] 16 bits CbCr[7:0] (odd) CbCr[7:0] (even) Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Cb6 Cr6 Cb8 Cr8
CbCr[4:0] (odd) 12 bits CbCr[4:0] (even)
Cb0[7:4] Cb0[3:0] Cb2[7:4] Cb2[3:0] Cb4[7:4] Cb4[3:0] Cb6[7:4] Cb6[3:0] Cb8[7:4] Cb8[3:0] Cr0[7:4] Cr0[3:0] Cr2[7:4] Cr2[3:0] Cr4[7:4] Cr4[3:0] Cr6[7:4] Cr6[3:0] Cr8[7:4] Cr8[3:0]
pixel clock * YCbCr, YUV, RGB [Y, Cb(U), Cr(V)]
Figure 18.3 YCbCr/RGB 4:4:4/4:2:2/4:2:0 Timing Diagram
Preliminary
18-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CAMERA INTERFACE
565RGB 16bits format
CLK HS Data_H[7:0] Data_L[7:0]
R0G0[5:3] R1G1[5:3] R2G2[5:3] R3G3[5:3] R4G4[5:3] R5G5[5:3] R6G6[5:3] R7G7[5:3] R8G8[5:3] R9G9[5:3] G0[2:0]B0 G1[2:0]B1 G2[2:0]B2 G3[2:0]B3 G4[2:0]B4 G5[2:0]B5 G6[2:0]B6 G7[2:0]B7 G8[2:0]B8 G9[2:0]B9
pixel clock * R and B channels are composed 5 bits and G channel is 6 bits.
565RGB 8bits format
CLK HS Data[7:0]
R0G0[5:3] G0[2:0]B0 R1G1[5:3] G1[2:0]B1 R2G2[5:3] G2[2:0]B2 R3G3[5:3] G3[2:0]B3 R4G4[5:3] G4[2:0]B4
pixel clock * 2 * R and B channels are composed 5 bits and G channel is 6 bits.
555RGB 16bits format
CLK HS Data_H[7:0] Data_L[7:0]
0R0G0[4:3] 0R1G1[4:3] 0R2G2[4:3] 0R3G3[4:3] 0R4G4[4:3] 0R5G5[4:3] 0R6G6[4:3] 0R7G7[4:3] 0R8G8[4:3] 0R9G9[4:3]
G0[2:0]B0 G1[2:0]B1 G2[2:0]B2 G3[2:0]B3 G4[2:0]B4 G5[2:0]B5 G6[2:0]B6 G7[2:0]B7 G8[2:0]B8 G9[2:0]B9
pixel clock * RGB channels are composed 5 bits and 1 bit is garbage. The garbage locates MSB or LSB 1bit. In figure, the garbage located MSB
555RGB 8bits format
CLK HS Data[7:0]
0R0G0[4:3] G0[2:0]B0 0R1G1[4:3] G1[2:0]B1 0R2G2[4:3] G2[2:0]B2 0R3G3[4:3]
G3[2:0]B30R4G4[4:3] G4[2:0]B4
pixel clock * 2 * RGB channels are composed 5 bits and 1 bit is garbage. The garbage locates MSB or LSB 1bit. In figure, the garbage located MSB
Bayer RGB format
CLK HS Data[7:0] (odd) Data[7:0] (even)
R G pixel clock G B R G G B R G G B R G G B R G G B
Figure 18.4 RGB 565/555/bayer Timing Diagram
Preliminary
18-4
TCC76x
18.3 Register Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CAMERA INTERFACE
Name CPCR 656FCR1 656FCR2 IICR1 IICR2 CDCR1 CDCR2 CDCR3 CDCR4 FIFOSTATE CIRQ ICCTRL
Table 18.2 CIF Register Map (Base Address = 0x80000B00) Address Type Reset Description 0x00 W 0x00000402 Color/Pattern Configuration Register 0x04 W 0x06FF0000 CCIR656 Configuration Register 1 0x08 W 0x0000010B CCIR656 Configuration Register 2 0x0C W 0x028001E0 Input Image Configuration Register 1 0x10 W 0x00000000 Input Image Configuration Register 2 0x14 W 0x00000003 CIF DMA Configuration Register 0x18 W 0x20000000 Memory Address for Y Channel 0x1C W 0x28000000 Memory Address for Cb(U) Channel 0x20 W 0x2C000000 Memory Address for Cr(V) Channel 0x24 R 0x00000000 FIFO Status Register 0x28 W/R 0x00000000 Interrupt & CIF Operating Register 0x2C W 0x00000000 Image Clock Control 0x80000B00 18 17 16 2 BO 1 HSP 0 VSP
Color/Pattern Configuration Register (CPCR) 31 30 29 28 27 26 25 24 23 22 21 20 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 RGBM<1:0> RGBBM<1:0> CS<1:0> BP BBS CP<1:0> PF<1:0> BP [15] 0 1 BBS [14] 0 1 CP [13:12] 00 01 10 PF [11:10] 00 01 10
RGBM [9:8]
19 3 0
Bypass Separated each channel data and stored into memory (default) Don't separate each channel data and stored into memory Bypass Bus Select Packing the data from MSB 8bits first in bypass 16bit mode (default) Packing the data from LSB 8bits first in bypass 16bit mode Color Pattern YCbCr color pattern (default) YUV color pattern RGB color pattern Pattern Format 4:4:4 format 4:2:2 format (default) 4:2:0 format or RGB mode RGB Mode
00 01 10
Bayer RGB mode (default) RGB555 mode RGB565 mode This mode is operated in RGB mode. RGB Bit Mode 16bit mode (4:2:0/4:2:2/4:4:4 YCbCr/YUV/GRB. RGB555/565 format) (default) 12bit mode (4:2:0 YCbCr/YUV), 8 bit disable sync (Non sync-port, CCIR656) 8 bit mode (Bayer/555/565RGB), 8 bit enable sync (sync-port, 4:2:2 format)
RGBBM [7:6]
00 01 10
Preliminary
18-5
TCC76x
CS [5:4]
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CAMERA INTERFACE
Color Sequence 555RGB 565RGB 4:4:4/4:2:2:/4:2:0 Bayer RGB CCIR656 00 RGB(MG) RGB R/Cb/U first BG->GR YCbYCr 01 RGB(LG) RGB R/Cb/U first GR->BG YCrYCb 10 BGR(MG) BGR B/Cr/V first RG->GB CbYCrY 11 BGR(LG) BGR B/Cr/V first GB->RG CrYCbY MG/LG of 555RGB item means MSB/LSB 1bit garbage. The sequence of Bayer RGB means that odd line is BGBGBG... and even line is GRGRGR.... at 00. Default value is 00. Bus Order Don't switch the MSB/LSB order (default) Switch the MSB/LSB order. Horizontal Sync Polarity Active low Active high (default) Vertical Sync Polarity Active low (default) Active high
BO [2] 0 1 HSP [1] 0 1 VSP [0] 0 1
CCIR656 Format Configuration Register 1 (656FCR1) 0x80000B04 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PSL<1:0> 0 FPV<7:0> 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPV<7:0> TPV<7:0> This register and next register (656FCR1 and 656FCR2) define the configuration of CCIR656. Figure 18.5 shows the control signals of this format.
S t a r t o f d i g it a l li n e HS F F EA V 00X 00Y 8 0 1 0 8 0 1 0 SAV F00 F00 X Y
S t a r t o f d i g it a l a c t iv e l in e C C I R 6 0 1 H s ig n a l C B Y C R Y C B Y
...Y
8 - b it d a t a D7 (M S B ) 1 p rea m b le s ta tu s 0 0 1 D6 1 0 0 F D5 1 0 0 V D4 1 0 0 H D3 1 0 0 P3 D2 1 0 0 P2 D1 1 0 0 P1 D0 1 0 0 P0
* S t a t u s w o r d d e f in e * F = ` 0 ' f o r f i e ld 1 , ` 1 ' f o r f i e ld 2 ( in t e r l a c e m o d e . If p r o g r e s s i v e , t h is v a l u e is ` 0 ' ) * V = ` 1 ' d u r i n g v e r t i c a l b la n k in g *H = `0 ' a t S A V , `1 ' a t E A V * P r o t e c t i o n b it s *P 3 = V x or H *P 2 = F x or H *P 1 = F x or V *P 0 = F x or V x or H
Figure 18.5 CCIR-656 Format Diagram
Preliminary
18-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CAMERA INTERFACE
PSL [26:25] Preamble and Status Location 00 The status word is located the first byte of EAV & SAV 01 The status word is located the second byte of EAV & SAV 10 The status word is located the third byte of EAV & SAV 11 The status word is located the forth byte of EAV & SAV If RGB bit mode is 8 bit disable mode, we must find the location of preamble and status for getting sync information. The total size of preamble and status is composed 4 bytes that preamble is 3 bytes and status is 1 byte. This register used to find the location of status word. FIELD FPV [23:16] SPV [15:8] TPV [7:0] Description First preamble value. Default value is 0xFF. Second preamble value. Default value is 0x00. Third preamble value. Default value is 0x00. 0x80000B08 18 17 16 2 1 VB<3:0> 0
CCIR656 Format Configuration Register 2 (656FCR2) 31 30 29 28 27 26 25 24 23 22 21 Reserved 15 14 13 12 11 10 9 8 7 6 5 Reserved HB<3:0> FIELD HB [8:5]
20 4 0
19 3
VB [3:0]
Description Horizontal blank In status word, location of `H' and H value at blanking. The MSB 3 bit means the location of `H', the other bit means value at blanking. Default value is 0x09. Vertical blank In status word, location of `V' and V value at blanking. The MSB 3 bit means the location of `V', the other bit means value at blanking. Default value is 0x0B
Input Image Control Register 1 (IICR1) 0x80000B0C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HSIZE <15:0> Horizontal size of input image. Default value is 0x0280. (decimal 640) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 VSIZE <15:0> Vertical size of input image. Default value is 0x01E0 (decimal 480) Input Image Control Register 2 (IICR2) 31 30 29 28 27 26 25 24 23 Reserved 15 14 13 12 11 10 9 8 7 HO <6:0> 0 FIELD HO [14:8] VO [6:0] 0x80000B10 18 17 16 1 0
22 6
21 5
20 4
19
3 2 VO <6:0>
Description Horizontal offset of input image in horizontal sync. Default value is 0x00. Vertical offset of input image in horizontal sync. Default value is 0x00.
Preliminary
18-7
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CAMERA INTERFACE
0x80000B14 18 17 16 2 Lock 1 0 BS <1:0>
CMOSIF DMA Configuration Register 1 (CDCR1) 31 30 29 28 27 26 25 24 23 22 Reserved 15 14 13 12 11 10 9 8 7 6 Reserved
21 5
20 4
19 3
BS [1:0] Preamble and Status Location 00 The DMA transfers the image data as 1 word to memory. 01 The DMA transfers the image data as 2 words to memory. 10 The DMA transfers the image data as 4 words to memory. 11 The DMA transfers the image data as 8 words to memory. (default) Using the burst of AMBA system. LOCK [2] 0 1 Lock Transfer Non-Lock (default) Lock Transfer
CMOSIF DMA Configuration Register 2 (CDCR2) 0x80000B18 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Y-ADDR[31:16] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Y-ADDR[15:0] In bypass mode, all data is stored to the base address defined by CDCR2 register. The other base address registers are ignored. CMOSIF DMA Configuration Register 3 (CDCR3) 31 30 29 28 27 26 25 24 23 22 Cb-ADDR[31:16] 15 14 13 12 11 10 9 8 7 6 Cb-ADDR[15:0] CMOSIF DMA Configuration Register 4 (CDCR4) 31 30 29 28 27 26 25 24 23 22 Cr-ADDR[31:16] 15 14 13 12 11 10 9 8 7 6 Cr-ADDR[15:0] FIELD Y-ADDR [31:0] Cb-ADDR [31:0] Cr-ADDR [31:0] 0x80000B1C 18 17 16 2 1 0
21 5
20 4
19 3
21 5
20 4
19 3
0x80000B20 18 17 16 2 1 0
Description Memory Base Address for Y(G) channel (Default = 0x20000000) Memory Base Address for Cb(U/R) channel (Default = 0x28000000) Memory Base Address for Cr(V/B) channel (Default = 0x2C000000)
Preliminary
18-8
TCC76x
FIFO States (FIFOSTATE) 31 30 29 28 27 26 15 14 13 12 11 10
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CAMERA INTERFACE
0x80000B24 18 17 16 2 FY 1 FC1 0 FC2
25 9
24 23 Reserved 8 7 RE WE
22 6 0
21 5 EY
20 4 EC1
19 3 EC2
There are three FIFOs; Y(G) channel, Cb(U/R) channel, Cr(V/B) channel FIFO. RE [8] 0 1 WE [7] 0 1 EY [5] 0 1 EC1 [4] 0 1 EC2 [3] 0 1 FY [2] 0 1 FC1 [1] 0 1 FC2 [0] 0 1 Read Error The empty signal is Low, or empty is High and read enable signal is Low. The empty signal and read enable signal are High. Read Error The full signal of FIFO is Low, or full is High and write enable signal is Low. The full signal of FIFO and write enable signal are High. Empty Signal from Y(G) Channel FIFO The state of Y(G) channel FIFO is non-empty. The state of Y(G) channel FIFO is empty. Empty Signal from Cb(U/R) Channel FIFO The state of Cb(U/R) channel FIFO is non-empty. The state of Cb(U/R) channel FIFO is empty. Empty Signal from Cr(V/B) Channel FIFO The state of Cr(V/B) channel FIFO is non-empty. The state of Cr(V/B) channel FIFO is empty. Full Signal from Y(G) Channel FIFO The state of Y(G) channel FIFO is non-full. The state of Y(G) channel FIFO is full. Full Signal from Cb(U/R) Channel FIFO The state of Cb(U/R) channel FIFO is non-full. The state of Cb(U/R) channel FIFO is full. Full Signal from Cr(V/B) Channel FIFO The state of Cr(V/B) channel FIFO is non-full. The state of Cr(V/B) channel FIFO is full.
Preliminary
18-9
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 CAMERA INTERFACE
0x80000B28 18 17 16 2 SII 1 0 0 ON
CMOSIF Interrupt Register (CIRQ) 31 30 29 28 27 26 25 15 14 13 12 11 Reserved 10 9
24 23 22 21 Reserved 8 7 6 5 PWDN 0 Pattern 0
20 4 RIQ
19 3 0
PWDN [8]
Camera Power Down Power down Power on Pattern Pattern off. Pattern on. Respond IRQ Don't acknowledge the Stored Image IRQ. Acknowledged the Stored Image IRQ. Stored Image IRQ Don't store the one frame image. Stored the one frame image. On/Off Can't operate CIF. Operating CIF (default)
0 1
Pattern [6]
0 1 RIQ [4] 0 1 SII [2] 0 1 ON [0] 0 1
Image Clock Control (ICCTRL) 31 30 29 28 27 26 25 15 14 13 12 11 10 9 Reserved
24 23 Reserved 8 7
22 6
21 5
20 4
19 3
0x80000B2C 18 17 16 2 1 CPH 0 CLK
DIV Divided Clock
DIV [3:2]
n
CPH [1]
Clock is divided by (n+1). Image Clock Phase 0 degree Shift 180 degree Usage Image Clock External clock Internal clock
0 1
CLK [0]
0 1
Preliminary
18-10
TCC76x
19 FAST GPIO 19.1 Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 FAST GPIO
In the TCC76x, there is special I/O facilities that enable high speed access for I/O port. These ports are shared with normal GPIO pins and can be accessed through some special instructions of dedicated coprocessor for these I/O. The dedicated coprocessor number is 5, so user can access these ports by using coprocessor instruction of ARM. Because there is no control signal to select between the two method (fast GPIO mode and normal GPIO mode), it is mandatory to clear one set of registers for these two method. For example, to use Fast GPIO, user must clear corresponding normal GPIO data and direction control register to zero, and vice versa. Besides of fast I/O port accessing, the dedicated coprocessor has additional functions for various purposes. It has bit-reversing functions on the 32bit or 12bit data. And it can calculate the number of leading zero of 32bit data. The following table shows coprocessor register for the above functions. Table 19.1 Register of Fast GPIO Description It is for I/O direction and I/O data control. Bit allocation of C0 register is as follows. C0[14:0] : FGPDATA(Fast GPIO Data Register) [14:0] FGPDATA[7:0] are shared with GPIO_A[7:0] FGPDATA[14:8] are shared with GPIO_A[14:8] / GPIO_D[21:15] C0[15] : Not used C0[30:16] : FGPCON(Fast GPIO Control Register) [14:0] C0[31] : Selection control for FGPDATA[14:8] path. 0 : FGPDATA[14:8] are shared with GPIO_D[21:15] 1 : FGPDATA[14:8] are shared with GPIO_A[14:8] It is for toggling C0 register bit-by-bit method. It is for accessing C1 register. It is for getting 32bit reverse information of C1 register. It is for getting 12bit reverse information of C1 register. It is for getting the number of leading zero of C1 register.
Name
Opcode1
C0
0
C1
1 0 1 2 3
To access the above registers, user must use the following instructions. Table 19.2 Instruction of CP5 Description To write Cn register as Rd value. To read Cn register on Rd register. To invert Fast GPIO, set certain bit field on Rd using this code. To get the 32bit-reverse of C1 register on Rd register. To get the 12bit-reverse of C1 register on Rd register. To get the number of leading zero in C1 register on Rd register.
Instruction MCR p5, 0, Rd, Cn, Cn, 0 MRC p5, 0, Rd, Cn, Cn, 0 MCR p5, 1, Rd, C0, C0, 0 MRC p5, 1, Rd, C1, C0, 0 MRC p5, 2, Rd, C1, C0, 0 MRC p5, 3, Rd, C1, C0, 0
Note:
Fast GPIO register access is guaranteed up to 90MHz of FCLK frequency. Do not access Fast GPIO reigisters when FCLK frequency exceeds the limit.
Preliminary
19-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 FAST GPIO
Preliminary
19-2
TCC76x
20 BOOTING PROCEDURE 20.1 Overview
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 BOOTING PROCEDURE
In the TCC76x, there is an internal boot ROM for system initialization process. It contains the fundamental routines for system initialization or boot procedure through various interface such as USB, NAND flash, and I2C. There are 5 modes for booting procedure. Figure 20.1 illustrates the timing of reset sequence at power-up. During this process, the boot mode is selected by the state of GPIO_B[24,22,21] at nRESET going to high. Table 20.1 represents the boot mode of the TCC76x.
VDDI VDDIO Xin/Xout nRESET tRST tBS GPIO_B [24,22,21] internal reset tBH Variable according to the application 217 number of Xin clock
BM[2:0]
tBH tBS tRST
: Hold time for boot mode setting. Minimum 10ns : Setup time for boot mode setting. Minimum 10ns : Time of reset activation must be maintained during power-up. Depending upon the stabilization time of crystal oscillator. Typically about 10us.
Figure 20.1 Reset Sequence
Preliminary
20-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 BOOTING PROCEDURE
BM[2:0] x1x
Table 20.1 Booting Mode of the TCC76x Description F/W download from USB interface If one of other boot processing (except external boot) fails, it starts this boot procedure automatically. I2C or NAND boot I2C interface using GPIO_D17 as I2C clock and GPIO_D16 as I2C data. NAND chip enable is controlled either by GPIO_A7 or A6 or D13 or D12, and NAND out-enable is controlled by nCS2. It can be used to attach serial EEPROM acquiring another function, or can remove NOR flash by put the F/W code in NAND flash. NOR boot, F/W download from USB I/F. NOR must be attached to nCS3 pin, and bus width can be configured
001
100
by GPIO_A[9:8]. NOR can contain encrypted code or normal code. If NOR code is corrupted, the TCC76x automatically changes to USB boot mode so user can fix NOR contents via USB interface. Development mode JTAG and SDRAM are enabled, and the base address of SDRAM is remained. The TCC76x is waiting for JTAG connection while toggling the GPIO_A[0] output. NOR boot without encryption NOR flash must be attached to nCS3 pin.
101
000
In the TCC760 and TCC761 the NOR flash is externally attached to nCS3. In the other TCC76x derivatives with on chip NOR flash, the nCS3 must be externally connected to FCSN pin.
20.2 External ROM Boot without Encryption (BM == 000)
It supports an external boot ROM. When external boot mode, the sequence begins from external ROM that is attached to nCS3. The bus width of external boot ROM can be determined by state of GPIO_A[9:8] at the rising edge of nRESET pin. If GPIO_A[9:8] == 0, the bus width is 16bit, if GPIO_A[9:8] == 1, it is 8bit, otherwise, it is 32bit. (Refer to the chapter of memory controller for more details)
Preliminary
20-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 BOOTING PROCEDURE
20.3 USB Boot (BM == x1x)
This mode is mainly for firmware upgrade mode. In this mode, user can download a program into internal SRAM and execute. The procedure of this mode is as follows. i) ii) iii) iv) v) vi) The TCC76x makes internal SRAM area starts from zero, and copies USB service routine to internal SRAM area. It change control flow from boot ROM to internal SRAM where the USB service routine just copied. It waits until USB connection is established. Once it is connected, host transfers first the parameter for USB loader routine including start address, destination address, and the amount of data to be transferred. The TCC76x starts communicating between a host PC with fixed amount of data which is called as packet. At every successful reception of packet, it copies that where the destination address pointed, and after all amount of data has been copied, it starts program where the start address pointed.
Normally, the program downloaded is for writing user system firmware to non-volatile memory like NOR or NAND flash. To use USB boot, the clock frequency of XIN must be 12MHz. The internal PLL is used to generate 48MHz of USB clock from XIN. The following figure illustrates the sequence of USB boot mode described above.
Mode Setting Set PLL for USB operation Set internal SRAM starts from zero
Copy USB service routine to SRAM JUMP to SRAM (0x00000000)
Connection Established ? Yes Receive the parameter for USB loader
No
Receive the packet Copy the packet to destination block No
All amount of Data ? Yes Jump to Start Address of USB loader
Figure 20.2 USB boot procedure
Preliminary
20-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 BOOTING PROCEDURE
20.4 I2C or NAND Boot (BM == 001)
There are 2 modes in the TCC76x when BM[2:0] is equal to 001. One is booting from serial EEPROM through I2C interface and the other is booting from NAND flash. The EEPROM must have I2C address of 0xA0 (for write) and 0xA1 (for read), and the NAND chip enable is controlled either by GPIO_A7 or GPIO_A6 or GPIO_D13 or GPIO_D12, and NAND out-enable is connected via nCS2 pin. The procedure checks if there exist EEPROM first, the I2C interface must be connected via GPIO_D17 for clock and GPIO_D16 for data. If there exist an EEPROM, the procedure follows I2C boot sequence or it checks if NAND flash is connected with some GPIO pins. The sequence of checking starts from GPIO_A7, then GPIO_A6, then GPIO_D13, and end with GPIO_D12. The boot sequence of I2C interface is as follows. i) Read init line from EEPROM. The init line consists of the following information. 1st word ~ 2nd word: security information 3rd word : size of code. ii) Check if the security information is correct. iii) Decrypt codes and copy them to internal SRAM (starts from 0x30000000). iv) After all amount of codes are decrypted and copied, the program executes from the start of internal SRAM (0x30000000). It is considered that the output enable of NAND flash is to be connected with nCS2. The boot sequence of NAND flash is as follows. Check if device id exist in the device id table while changing chip select pin from GPIO_A7 to GPIO_D12. (GPIO_A7 GPIO_A6 GPIO_D13 GPIO_D12) ii) Set CSCFG2 register according to device id value. iii) Read data by 512 bytes unit from the last page down to half of NAND size until the ECC (SSFDC standard) of them and the 1st and 2nd word in them are all correct. Select lower or upper half of 512 bytes as an initialization code block according to the result of ECC checking. 1st word ~ 2nd word: security information. iv) If the correct block is found, copy the remaining of code in selected block from the 3rd word to internal SRAM (starts from 0x30000000). After all amount of codes are copied (initialization codes are not encrypted), the program sequence is changed to internal SRAM (0x30000000). And these codes take responsibility of the remaining boot process. The overall flow of I2C and NAND boot is illustrated in the Figure 20.3 The supported NAND flash types are as follows. i)
Preliminary
20-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 BOOTING PROCEDURE
Table 20.2 Supported NAND flash types Size Size of Page Number Device ID CADR (bytes) (bytes) of Page x8 / x8 / x16 / x16 8M 16M 32M 64M 128M 256M 512M 128M 256M 512M 1G 2G 512 512 512 512 512 512 512 2048 2048 2048 2048 2048 16K 32K 64K 128K 256K 512K 1024K 64K 128K 256K 512K 1024K 3 3 3 4 4 4 4 4 5 5 5 5 39 / E6 / 49 / 59 33 / 73 / 43 / 53 35 / 75 / 45 / 55 36 / 76 / 46 / 56 78 / 79 / 72 / 74 71 DC A1 / F1 / B1 / C1 AA / DA / BA / CA AC / DC / BC / CC A3 / D3 / B3 / C3 A5 / D5 / B5 / C5
Check If serial EEPROM is attached
Attached ? Yes Read Init Line (1st 4 words)
No
NAND Device code reading through nCS2
No
Device Code OK ? Yes
Init Line is OK ? Yes Read initialization codes & Decrypt them. Copy to SRAM (0x30000000)
No
CSCFG2 Register Setting N = last page number
Yes JUMP to SRAM (0x30000000)
Over the Half of NAND size ? No Read 512 bytes to buffer N=N-1
USB Boot Mode ECC is OK ? Yes 1st & 2nd word are OK ? Yes Copy initialization code from buffer to SRAM JUMP to SRAM (0x30000000) No No
Figure 20.3 I2C and NAND boot procedure
Preliminary
20-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 BOOTING PROCEDURE
20.5 External ROM Boot with Encryption (BM == 100)
The NOR flash must be connected via nCS3 signal. The boot sequence of this mode is as follows. Read init line from NOR flash. The init line consists of the following information. 1st word ~ 2nd word: security information 3rd word : size of initialization code. ii) If 1st or 2nd word is 0xFFFFFFFF, it goes to USB boot mode for F/W downloading. iii) If 1st and 2nd word don't contain security information, then it calculates CRC-32 for the 1st 512kbytes of NOR flash and compare the CRC-32 code with 6th word of NOR flash. If the CRC checking is success, it goes to external NOR boot by jumping 0x70000000. Or if the CRC check is failed, it goes to USB boot mode for F/W downloading. iv) If the 1st and 2nd word are correct, read initialization code from the next data of init line, and copy them to internal SRAM (starts from 0x30000000). After all amount of codes are copied (initialization codes are not encrypted), the program make a call (branch with link) command to internal SRAM (0x30000000). The initialization code must be encapsulated by the entrance command of `STR LR, [SP - #4]!', and the exit command of `LDR PC, [SP], #4'. v) The initialization code must make arrange the memory area so that the zero base area (0x00000000 ~ 0x0FFFFFFF) can contain the main F/W code and then goes back to booting sequence while setting r0 register to the start address of F/W code. vi) Read the size of F/W code at the address designated by r0 register. vii) The F/W code is read from the next address of the r0 register and decrypted and copied to the zero base area (0x00000000 ~ 0x0FFFFFFF). viii) After all of amount of F/W codes are decrypted and copied, the program jumps to 0x00000000. Figure 20.4 illustrates the allocation map of encrypted F/W code in NOR flash.
4 byte 0x70000000 0x70000010 Init Line of NOR flash S0 S1 SA
i)
Initialization Code Area (SA bytes) . . . Returning from these area, the register R0 contains the start address of F/W code
R0
Size of F/W SB Main F/W Code Area (SB bytes)
Figure 20.4 Allocation of encrypted F/W code
Preliminary
20-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 BOOTING PROCEDURE
20.6 Development mode (BM == 101)
To ease the effort for starting development with the TCC76x, the TCC76x provides development mode in booting. In this mode, JTAG and SDRAM interface are enabled and set protection unit of the TCC76x appropriately. The Table 20.3 describes the region setting in this mode. Table 20.3 Region Settings in Development Mode End I Cache D Cache Buffer Protection
Region # 0 1 2 3 4 5 6 7
Start
0x00000000 0xFFFFFFFF Disabled Disabled Disabled Full Access 0x20000000 0x3FFFFFFF Disabled Disabled Disabled Full Access 0x40000000 0x4FFFFFFF Disabled Disabled Disabled Full Access 0x50000000 0x5FFFFFFF Disabled Disabled Disabled Full Access 0x60000000 0x6FFFFFFF Disabled Disabled Disabled Full Access 0x70000000 0x7FFFFFFF Disabled Disabled Disabled Full Access 0x80000000 0xFFFFFFFF Disabled Disabled Disabled Full Access 0x3000F000 0x3000FFFF Disabled Disabled Disabled Full Access *) The region of higher number has higher priority than that of other regions. So region 7 has highest priority and region 0 has lowest priority. After region setting finishes, it goes into a infinite loop while toggling GPIO_A[0].
Preliminary
20-7
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 BOOTING PROCEDURE
Preliminary
20-8
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 JTAG DEBUG INTERFACE
21 JTAG DEBUG INTERFACE
The TCC76x has the ARM940T core as main controller, and JTAG interface for developing the application programs. It can be connected with OPENice32 of AIJI System or Multi-ICE of ARM or other third party's in-circuit emulator supporting for ARM940T core. With the use of in-circuit emulator, users can easily develop the program for their own system. It provides hardware breakpoints, internal register monitoring, memory dump, etc. Refer to user's manual of in-circuit emulator for more detail functions of it. Figure 21.1 shows the application circuit for JTAG interface. Care must be taken not to combine system reset with JTAG reset signal.
20 18 16 14 12 10 8 6 4 2
19 17 15 13 11 9 7 5 3 1
VDDIO nSRST TDO TCK TMS TDI nTRST 10K 10K 10K 10K TDO TCK TMS TDI
TCC76x RESET CIRCUIT
nTRST nRESET
Figure 21.1 JTAG Interface Circuit Diagram
Preliminary
21-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 JTAG DEBUG INTERFACE
21.1 Debugging with OPENice32 & AIJI Spider
OPENice32 is a powerful and convenient emulator for ARM processor. It provides the best debugging solution for Telechips ARM processor, TCC76x series. A powerful debugger, AIJI Spider, is supplied with OPENice32. It also provides a TCC76x device file and flash device file. To debug the target system using TCC76x with OPENice32, you should set the Boot Mode as development mode. Refer to the Boot Procedure chapter to set the Boot Mode. For more information, refer to OPENice32 manual or application note. System Configuration OPENice32 is connected to the host PC with serial, USB or Ethernet that provides high speed downloading. It is connected to the target JTAG connector with a 20-way cable.
USB/Ethernet
OPENice32
JTAG TCC76X
Telechips
Host PC
OPENice32
Target System
Figure 21.2 Connection between Host PC and OPENice32 and Target System
Preliminary
21-2
TCC76x
JTAG connector on the target
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 JTAG DEBUG INTERFACE
The following diagram shows the JTAG connector on a target system and a 20-14pinadapter board. When designing a target board, users can select a 14pin header or 20pin header. The pin configuration of header on the target board should be same as following diagram.
T_VCC nTRST TDI TMS TCK x TDO nSYSRST x x
1 3 5 7 9 11 13 15 17 19
2 4 6 8 10 12 14 16 18 20
x GND GND GND GND GND GND GND GND GND T_VCC nTRST TDI TMS TCK TDO T_VCC 1 3 5 7 9 11 13 2 4 6 8 10 12 14 GND GND GND GND GND nSYSRST GND
[20 pin Connector]
[14 pin Connector]
Figure 21.3 Pin Configuration of 20 and 14 pin Connector
OPENice32 Interface
[20-14 Adapter]
Figure 21.4 20-14 Adapter Board
Contact Point
If you have any question regarding OPENice32, please contact AIJI System. AIJI System.Co., Ltd. Tel: +82-32-223-6611 email:stroh@aijisystem.com http://www.aijisystem.com http://www.mculand.com
Preliminary
21-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 JTAG DEBUG INTERFACE
Preliminary
21-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB 2.0 & CARD INTERFACE
22 USB 2.0 & CARD INTERFACE
This section describes USB 2.0 device controller and Memory Card Interface block in the TCC766 and TCC767.
22.1 Overview
*
USB 2.0 Interface USB Specification 2.0 & 1.1 Compliant Supports High Speed Transfers (480Mbit/sec) Supports Full Speed Transfers (12Mbit/sec) Supports Four Endpoints : Endpoint 0 : 64 Bytes CONTROL transfer Endpoint 1 : 512*2 Bytes BULK IN transaction Endpoint 2 : 512*2 Bytes BULK OUT transaction Endpoint 3 : 64 Bytes INTERRUPT IN transaction
*
Memory Card Interfaces Memory Stick (MS) Memory Stick PRO(MSPRO) SecureDigital Card (SD) MultiMedia Card (MMC) Build-in NAND Flash Memory
*
Memory Stick / Memory Stick PRO Interface Fully compatible with the Memory Stick Standard Format Specification Version 1.4 Fully compatible with the Memory Stick PRO Standard Format Specification Version 1.00 Auto Data CRC generating & checking Memory Stick Support capacity 4/8/16/32/64/128MB Memory Stick PRO Support capacity 256/512/1024MB
*
Secure Digital Card / MultiMedia Card Interface Fully compatible with MultiMediaCard System Specification 3.0 Fully compatible with Secure Digital Specification 1.01 MMC Support capacity 4/8/16/32/64/128MB SD Support capacity 4/8/16/32/64/128/256/512MB Auto Data CRC generating & checking Auto Command/Response CRC generating & checking Standard MMC/SPI/SD 4-bit mode interface support
*
Build-In NAND Flash Memory Interface Build-in hardware ECC circuit (Hamming & Reed-Solomon). Support SLC(Single Level Cell) NAND Flash Memory. Ex: 128Mb,256Mb,512Mb,1Gb. Support Big Block(2K+64 Bytes per page) NAND Flash Memory. Ex: 1Gb, 2Gb, 4Gb. Support MLC(Multi Level Cell) NAND flash. Ex: 512Mb, 1Gb.
Preliminary
22-1
TCC76x
22.2 Register Description
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB 2.0 & CARD INTERFACE
Table 22.1 I/O Port Functions and Selection Addresses
nCS0 1 nCS1 1 Addresses A2 X A1 X A0 X Functions Read (nIOR) Write (nIOW) Data bus high impedance Not used Control block registers Data bus high impedance Not used Data bus high impedance Not used Alternate Status Device Control Obsolete Not used Command block registers Data Data Error Features Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device/Head Device/Head Status Command Invalid address Invalid address
1 1 1 1 0 0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1 1 1 1 1 0
0 1 1 1 0 0 0 0 1 1 1 1 X
X 0 1 1 0 0 1 1 0 0 1 1 X
X X 0 1 0 1 0 1 0 1 0 1 X
Table 22.2 The Relationship of MST[2:0] Pins and Feature Register
MST[2:0] Configuration Feature register
111 001 010
Record in flash memory by AP. In USB Mode, First slot is NAND Flash memory, Second slot is MMC/SD and Third slot is MS/MS Pro/New MS card
Only support MMC/SD card Only support MS/MS_Pro card Support two kinds of card above. And MMC/SD is 011 the first slot in USB mode. Support two kinds of card above. And MS/MS_Pro 100 card is the first slot in USB mode. Value of Feature register is slot number of each memory. Fill feature register before access command
0x80: direct to Flash Memory Hidden disk 0x00: direct to NAND Flash Memory FAT disk. 0x01: direct to MMC/SD card 0x02: direct to MS/MS Pro card 0x00: direct to MMC/SD card 0x00: direct to MS/MS Pro card 0x00: direct to MMC/SD card 0x01: direct to MS/MS Pro card 0x00: direct to MS/MS Pro card 0x01: direct to MMC/SD card
After Feature register has been filled, Initial Media Command(0x62) should be issued.
Preliminary
22-2
TCC76x
22.3 IDE Commands
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB 2.0 & CARD INTERFACE
Table 22.3 Summary of IDE Commands
Command Name ReCalibrate ReadSectors WriteSectors ReadVerify Seek TranslateSector Diagnostics ReadMultiple WriteMultiple SetMultiple ReadBuffer WriteBuffer AtaIdentifyDrive IDEGetMaxLun ATACheckMedia ATAInitial GetSerialNumber SetIDESuspend Command Code 0x1F 0x20 0x30 0x40 0x70 0x87 0x90 0xC4 0xC5 0xC6 0xE4 0xE8 0xEC 0x60 0x61 0x62 0x63 0x64 Description
Standard Command
Refer to ATA/ATAPI-4 Standard.
Vendor Command
Get Maximum number of LUN value. Check Media Status. Initialize Media. Read Serial Number(16bytes), VID and PID. Go to Suspend Mode.
22.3.1 Standard Commands
The Commands except PACKET and SERVICE commands are listed in Table 22.3. Standard for detailed description. Refer to the ATA/ATAPI-4
22.3.2 Vendor Commands
There are five vendor commands as described in the following table. should be written.
Name IDEGetMaxLun
Before access command, Feature register
Table 22.4 Vendor Commands
Code Protocol Input Output Description 0x60 Non-data None Number Get slot number. Register Sector Number will response how many slot is of slots supported. ATACheckMedia 0x61 Non-data None Media Check media connection. Error register response media status. status Definition of error register: if bit 1 is true, and if bit 4 is true. no media insert, else (false) media is insert if bit 5 is true, media write protect, else (false) media write enable if bit 6 is true, media initial failed, else (false) media initial pass if bit 7 is true, same with bit 4 if bit 1 is false, and if bit 5 is true, media change, (memory card already been change, need to initial command 0x62) ATAInitial 0x62 Non-data None None Initialize Media. After power on or media change, Initial media command must be executed. Read Serial Number(16bytes), VID and PID. It is some control flow with GetSerialNumber 0x63 PIO data None 512 in Bytes of command 0xEC. 512 bytes will be sent out as follows, S/N, Byte Description VID and 0 Valid serial number length PID 1 ~ 24 Serial Number (valid data is according length) 25 VID (Low Byte) 26 VID(High Byte) 27 PID(Low Byte) 28 PID(High Byte) SetIDESuspend 0x64 Non-data None None When this command is accessed, it will go to suspend mode and force pin ACT_nSPND low. When next IDE command access, it will auto wake up and force pin ACT_nSPND high.
Preliminary
22-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 USB 2.0 & CARD INTERFACE
Preliminary
22-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ELECTRICAL SPECIFICATION
23 ELECTRICAL SPECIFICATION
Unless otherwise specified, all the electrical specifications are valid only for the TCC760 / TCC761 signals.
23.1 Absolute Maximum Ratings
Table 23.1 Absolute Maximum Ratings
Parameter Symbol Rating Unit
DC Supply Voltage for 3.3V I/O DC Supply Voltage for 1.8V I/O DC Supply Voltage for Internal Digital Logic DC Supply Voltage for Analog Part of ADC DC Supply Voltage for PLL Digital Input Voltage for 3.3V Input Buffer Digital Input Voltage for 1.8V Input Buffer Analog Input Voltage for ADC DC Input Current Storage Temperature
Notes: 1.
VDDIO VDD_OSC VDDI VDDA_ADC VDDA_PLL VIN VIN_OSC VINA IIN TSTG
3.8 2.5 2.5 3.8 2.5 4.6 2.5 0 ~ VDDA_ADC +/- 200 -45 to 125
V V V V V V V V mA
o
C
2. 3. 4.
Absolute maximum ratings specify the values beyond which the device may be damaged permanently. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and functional operation under any of these conditions is not implied. All voltages are measured with respect to VSS unless otherwise specified. VDDI must always be less than or equal to VDDIO or VDD_OSC VDD_OSC must always be less than or equal to VDDIO
23.2 Recommended Operating Conditions
Table 23.2 Recommended Operating Conditions
Parameter Symbol MIN TYP MAX Unit
DC Supply Voltage for 3.3V I/O (TCC760/TCC761 only) DC Supply Voltage for 3.3V I/O DC Supply Voltage for 1.8V I/O DC Supply Voltage for Internal Digital Logic DC Supply Voltage for Analog Part of ADC DC Supply Voltage for PLL Digital Input Voltage for 3.3V Input Buffer Digital Input Voltage for 1.8V Input Buffer Digital Output Voltage Analog Input Voltage for ADC External Loop Filter Capacitance for PLL Operating Temperature
VDDIO VDDIO VDD_OSC VDDI VDDA_ADC VDDA_PLL VIN VIN_OSC VOUT VINA LF TOPER
1.65 2.7 1.65 1.65 3.0 1.65 -0.1 -0.1 -0.1 0.0 315 -30
350
3.6 3.6 1.95 1.95 3.6 1.95 VDDIO + 0.15 VDD_OSC + 0.15 VDDIO + 0.15 VDDA_ADC 385 85
V V V V V V V V V V pF
o
C
Preliminary
23-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ELECTRICAL SPECIFICATION
23.3 Electrical Characteristics
Table 23.3 Electrical Characteristics
Parameter Symbol Test Conditions MIN TYP MAX Unit
High Level Input Voltage Low Level Input Voltage Schmitt Trigger, Positive-going Threshold Schmitt Trigger, Negative-going Threshold High Level Input Current Low Level Input Current Low Level Input Current (pull-up enabled)
VIH VIL VT+ VTIIH IIL
VDDIO = 3.3V0.3V VDDIO = 1.8V 0.15V VDDIO = 3.3V0.3V VDDIO = 1.8V 0.15V VDDIO = 3.3V0.3V VDDIO = 1.8V 0.15V VDDIO = 3.3V0.3V VDDIO = 1.8V 0.15V VIN = VDDIO VIN = VSS VDDIO = 3.3V0.3V
0.7 VDDIO 0.8 VDDIO 0.8 0.57 2.0 1.27 0.8 0.57 -10 -10 -66 2.4 1.1 0.4 0.5 -10 10 10 10 32 40 100 3 20 5 50 150
0.8 1.0 1.0 2.0
V V V V V V V V 10 10 -33 -10
A A A
High Level Output Voltage
VOH
IOH = -4/6/8/12mA VDDIO = 1.8V 0.15V IOH = -2/3/4/6mA VDDIO = 3.3V0.3V IOL = 4/6/8/12mA VDDIO = 1.8V 0.15V IOL = 2/3/4/6mA VOUT = VSS or VDDIO VDDIO = 3.3V, No Load VIN = VSS or VDDIO
V V V V
A A
Low Level Output Voltage
VOL
Tri-state Output Leakage Current Quiescent Supply Current for I/O XIN/XOUT Operating Frequency XTIN/XTOUT Operating Frequency PLL Dynamic Current PLL Power Down Current PLL Input Frequency PLL Output Frequency PLL Locking Time ADC Differential Nonlinearity ADC Integral Nonlinearity ADC Offset Voltage Error (Top / Bottom) ADC Maximum Conversion Rate ADC Dynamic Current ADC Standby Supply Current
IOZ IDS_IO FOSC1 FOSC2 IDD_PLL IPD_PLL FIN_PLL FOUT_PLL TLT DNL INL EOT/EOB fC IDD_ADC IPD_ADC
MHz kHz mA
A
VDDA_PLL = 1.8V VDDA_PLL = 1.8V VDDA_PLL = 1.8V VDDA_PLL = 1.8V VDDA_PLL = 1.8V VDDA_ADC = 3.3V VDDA_ADC = 3.3V VDDA_ADC = 3.3V fCKIN = 2.5 MHz VDDA_ADC = 3.3V VDDA_ADC = 3.3V
50 500
MHz MHz
s
LSB LSB LSB KSPS mA
A
3.0
8.0 500 4 20
Ta = 25oC, VDDIO = VDDA_ADC = 3.3V0.3V, VDD_OSC = VDDA_PLL = VDDI = 1.8V0.15V, VSSIO = VSSI = VSSA_PLL = VSSA_ADC = 0.0V unless otherwise specified. VDDIO = 1.8V 0.15V condition is valid only for the TCC760 and TCC761.
Not all parameters are tested. Guaranteed by design characterization.
Preliminary
23-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ELECTRICAL SPECIFICATION
23.4 Absolute Maximum Ratings - NOR Flash
Table 23.4 Absolute Maximum Ratings - NOR Flash
Parameter Symbol Rating Unit
DC Supply Voltage for NOR Flash Input Voltage for NOR Flash DC Input Current for NOR Flash Storage Temperature
VDD_NOR VIN_NOR IIN_NOR TSTG_NOR
-0.5 to 3.8 -0.5 to VDD_NOR + 0.5 +/- 100 -45 to 85
V V mA
o
C
The voltage difference between VDDIO and VDD_NOR must always be within 0.3V
23.5 Recommended Operating Conditions - NOR Flash
Table 23.5 Recommended Operating Conditions - NOR Flash
Parameter Symbol MIN TYP MAX Unit
DC Supply Voltage for NOR Flash Input Voltage for NOR Flash Operating Temperature for NOR Flash
VDD_NOR VIN_NOR TOPER_NOR
2.7 -0.1 0
-
3.6 VDD_NOR + 0.15 70
V V
o
C
23.6 Electrical Characteristics - NOR Flash
Table 23.6 Electrical Characteristics - NOR Flash
Parameter Symbol Test Conditions MIN TYP MAX Unit
High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current High Level Output Voltage Low Level Output Voltage Output Leakage Current Supply Current Stanby Supply Current Endurance
VIH_NOR VIL_NOR IIH_NOR IIL_NOR VOH_NOR VOL_NOR IOZ_NOR IDD_NOR IDS_NOR
VDD_NOR = 3.3V0.3V VDD_NOR = 3.3V0.3V VIN_NOR = VDD_NOR VIN_NOR = VSS_NOR VDD_NOR = VDD_NOR_MIN IOH_NOR = -100A VDD_NOR = VDD_NOR_MIN IOL_NOR = 100A VOUT_NOR = VSS_NOR or VDD_NOR Read Program / Erase FCSN = VDD_NOR Program / Erase
0.7 VDD_NOR 0.8 -10 -10 VDD_NOR - 0.2 0.2 -10 10 30 30 3 100,000 20 10 10
V V
A A
V V
A
mA mA
A
Cycles
Ta = 25oC, VDD_NOR = VDDIO = 3.3V0.3V, VSS_NOR = VSSIO = 0.0V unless otherwise specified.
Table 23.7 AC Characteristics - NOR Flash
Parameter Symbol Test Conditions MIN TYP MAX Unit
Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output High-Z
tRC tAA tCE tOE tCHZ FCSN = nOE = VSS_NOR nOE = VSS_NOR FCSN = VSS_NOR
70 70 70 35 25
ns ns ns ns ns
Preliminary
23-3
TCC76x
Parameter
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ELECTRICAL SPECIFICATION
Symbol
Test Conditions
MIN
TYP
MAX
Unit
Output Enable to Output High-Z Output Hold Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Chip Enable Setup Time Chip Enable Hold Time Output Enable Setup Time Output Enable Hold Time Write Enable Pulse Width Write Enable Pulse Width High
Notes:
tOHZ tOH tAS tAH tAS tAH tCS tCH tOES tOEH tWP tWPH 0 0 45 35 0 0 0 0 10 40 30
25
ns ns ns ns ns ns ns ns ns ns ns ns
1. 2. 3.
Measurement Condition: CL = 30pF, Input Rise/Fall Time = 5.0ns Before accessing the NOR Flash, the CSCFG3 register must be programmed appropriately to meet the above timing parameters. (Refer to section "Memory Controller"). Actual access timing is determined by the value of the CSCFG3 register and Memory Controller clock (HCLK) frequency.
Not all parameters are tested. Guaranteed by design characterization.
Preliminary
23-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ELECTRICAL SPECIFICATION
23.7 Absolute Maximum Ratings - Audio CODEC
Table 23.8 Absolute Maximum Ratings - Audio CODEC
Parameter Symbol Rating Unit
Digital Supply Voltage for Audio CODEC Analog Supply Voltage for Audio CODEC Digital Input Voltage for Audio CODEC Analog Input Voltage for Audio CODEC Storage Temperature for Audio CODEC
Notes:
VDDC_CDC VDDB_CDC VDDA_CDC VIN_CDC VINA_CDC TSTG_CDC
-0.3 to 3.63 -0.3 to 3.63 -0.3 to VDDB_CDC + 0.3 -0.3 to VDDA_CDC + 0.3 -45 to 125
V V V V
o
C
1. 2. 3. 4. 5.
The voltage difference between analog and digital grounds (VSS_CDC, AGND) must always be within 0.3V. VDDA_CDC includes AVDD and HPVDD. VDDC_CDC must not exceed VDDA_CDC or VDDB_CDC VDDB_CDC must not exceed VDDA_CDC The voltage difference between VDDIO and VDDB_CDC must always be within 0.3V
23.8 Recommended Operating Conditions - Audio CODEC
Table 23.9 Recommended Operating Conditions - Audio CODEC
Parameter Symbol MIN TYP MAX Unit
Digital Supply Voltage for Audio CODEC (Core) Digital Supply Voltage for Audio CODEC (Buffer) Analog Supply Voltage for Audio CODEC Digital Input Voltage for Audio CODEC Analog Input Voltage for Audio CODEC Operating Temperature for Audio CODEC
VDDC_CDC VDDB_CDC VDDA_CDC VIN_CDC VINA_CDC TOPER_CDC
1.42 2.7 2.7 -0.1 -10
1.5 3.3 3.3 1
3.6 3.6 3.6 VDDB_CDC + 0.15 70
V V V V VRMS
o
C
23.9 Electrical Characteristics - Audio CODEC
Ta = 25oC, VDDA_CDC = VDDB_CDC = 3.3V, VDDC_CDC = 1.5V, VSSA_CDC = 0.0V, Fs = 48kHz unless otherwise specified.
Table 23.10 Electrical Characteristics - Audio CODEC Digital I/O
Parameter Symbol Test Conditions MIN TYP MAX Unit
High Level Input Voltage Low Level Input Voltage High Level Input Current High Level Input Current (pull-down enabled) Low Level Input Current Low Level Input Current (pull-up enabled) High Level Output Voltage Low Level Output Voltage
VIH_CDC VIL_CDC IIH_CDC
VDDB_CDC = 3.3V VDDB_CDC = 3.3V VDDB_CDC = 3.3V VIN_CDC = VDDB_CDC VDDB_CDC = 3.3V VIN_CDC = VSS_CDC VDDB_CDC = 3.3V VDDB_CDC = 3.3V
0.7 VDDB_CDC 0.3 VDDB_CDC -10 -10 -10 -90 0.9 VDDB_CDC 0.1 VDDB_CDC 10 90 10 10
V V
A A A A
IIL_CDC VOH_CDC VOL_CDC
V V
Preliminary
23-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 ELECTRICAL SPECIFICATION
Table 23.11 Electrical Characteristics - Audio CODEC Analog
Parameter Symbol Test Conditions MIN TYP MAX Unit
SNR of Line Input THD of Line Input SNR of MIC_IN THD of MIC_IN SNR of Line Output THD of Line Output Headphone Max Output Power SNR of Headphone Out THD of Headphone Out
SNRLI THDLI SNRM THDM SNRLO THDLO Po SNRH THDH
A-weighted, 0dB Gain -1dB Input, 0dB Gain A-weighted, 0dB Gain 0dB Input, 0dB Gain A-weighted, Load = 10k, 50pF 1kHz, 0dB, Load = 10k, 50pF RL = 16 A-weighted 1kHz, Po = 10mW 1kHz, Po = 20mW
90 -80 84 -60 100 -88 50 90 0.1 1.0 -80
dB dB dB dB dB dB mW dB % %
Table 23.12 Electrical Characteristics - Audio CODEC Power
Parameter Symbol Test Conditions MIN TYP MAX Unit
Supply Current Static Current
Notes:
IDD_CDC IDS_CDC
Record and playback (all active) No input signal Power down, Clock stopped No input signal
24 10
mA
A
1.
The power dissipation in the headphone is excluded.
Not all parameters are tested. Guaranteed by design characterization.
Preliminary
23-6
TCC76x
24 PACKAGE DIMENSIONS
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 PACKAGE DIMENSIONS
24.1 TCC760 Package Dimension
16.00BSC 14.00BSC
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1 ~ 7o
0.10
+0.10 -0.01
97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48
16.00BSC 14.00BSC
TCC760
47 46 45 44 43 42 41 40 39 37 36 35 33 34 38
0.40BSC
0.18 0.05
(0.80) 0.10 1.00 0.05 0.05
Figure 24.1 TCC760 Package Dimension (128-TQFP-1414)
Preliminary
0.60 1.20MAX
24-1
0.15
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 PACKAGE DIMENSIONS
24.2 TCC761 Package Dimension
24.2.1 TCC761-E Package Dimension
30.00 28.00
0.30 0.20
0 ~ 8o
0.127
+0.10 -0.05
0.50
0.20
+0.10 -0.05
(1.25) 0.10 1.40 0.05 0.10
Figure 24.2 TCC761-E Package Dimension (208-LQFP-2828)
Preliminary
0.50 1.60MAX
24-2
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 205 206 208
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
TCC761-E
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
30.00 28.00
0.30 0.20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
0.20
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 PACKAGE DIMENSIONS
24.2.2 TCC761-Y Package Dimension
15.00 0.45 0.05
15.00
TCC761Y
12.80TYP 6.40 1.10TYP
#A1 Index Mark 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
0.32 1.00
0.05
0.80TYP
1.10TYP
0.80TYP
ABCDEFGHJKLMNPRTU
Figure 24.3 TCC761-Y Package Dimension (208-TBGA-1515)
Preliminary
24-3
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 PACKAGE DIMENSIONS
24.3 TCC763 / TCC764 Package Dimension
10.00 0.40TYP
10.00
TCC763 / TCC764
8.80
0.33
0.05
1.50MAX 0.60TYP
#A1 Index Mark 1 2 3 4 5 6 7 8 9 10 11 12
0.80
0.60TYP
0.80
A
B
C
D
E
F
G
H
J
K
L
M
Figure 24.4 TCC763 / TCC764 Package Dimension (144-FPBGA-1010)
Preliminary
24-4
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 PACKAGE DIMENSIONS
24.4 TCC766 Package Dimension
(4X)
14.00 A1 BALL PAD CORNER
5.
0.40 TYP
14.00
6.
SEATING PLANE
0.33 + 0.05 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C 0.80 E F G H J K L M N P R (1.00) T D 1.10 + 0.05 1.64 + 0.10
(1.00)
0.80
Figure 24.5 TCC766 Package Dimension (232-FPBGA-1414)
Preliminary
24-5
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 PACKAGE DIMENSIONS
24.5 TCC767 Package Dimension
13.00
A1 BALL PAD CORNER
0.40 0.05
13.00
0.33 0.05
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A B C
1.10 0.05 1.64 0.10
0.80
D E F G H J K L M N P R 0.90
0.90
0.80
Figure 24.6 TCC767 Package Dimension (225-FPBGA-1313)
Preliminary
24-6
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 PACKAGE DIMENSIONS
24.6 TCC768 Package Dimension
10.00 0.40TYP
10.00
TCC768
0.33 1.64 A1 BALL PAD CORNER 12 10 8 6 4 2
0.05 0.10
11
9
7
5
3
1 A B C D E F G H J
0.80
0.60 L
K M 0.60 0.80
Figure 24.7 TCC768 Package Dimension (144-FPBGA-1010)
Preliminary
24-7
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 PACKAGE DIMENSIONS
Preliminary
24-8
TCC76x
25 TCC76x vs. TCC72x 25.1 Feature Comparison
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TCC76X VS. TCC72X
Table 25.1 Feature Comparison
Item
Process / Typical Core Voltage CPU CPU Frequency SDRAM clock frequency DDR SDRAM support ECC Generation Camera Interface Color Space Converter for LCD 16-bpp Mode for STN LCD DMA Controller Fast GPIO Controller I2C Master DAI Buffer Size CDIF Buffer Size 32-bit Counter IDLE/Power Down Mode Clock USB Device EP0 FIFO size ADC Core PLL Core Max. Frequency On-Chip Audio CODEC
TCC721
0.25m / 2.5V ARM940T 120MHz 50MHz Software only 1 Channel Software only 2x4 4 XIN(12MHz) 16Bytes 500KSPS / 10bit / 2.5V 300MHz Yes
TCC761
0.18m / 1.8V ARM940T 140MHz 100MHz 100MHz Hardware ECC for SLC NAND, AGAND Optional CCIR656 Input YUV-to-RGB / RGB-to-YUV Supported (RGB444) 2 Channel Supports up to 15 GPIO pins Hardware I2C Master Core 2x8 8 Programmable down to 1Hz XIN(12MHz) or XTIN (32.768kHz) 64Bytes 500KSPS / 10bit / .3.3V 500MHz -
Note
Optional Pins shared with GPIOs
Shared with GPIO_A, D pins Pins shared with GPIOs
Means CPU clock source.
25.2 Pin Comparison
Table 25.2 Power Voltage Range Comparison
Pin Name
VDDIO VDD_NOR
TCC72x
2.7 ~ 3.3 V 2.7 ~ 3.3 V
TCC76x
1.8 ~ 3.3 V 2.7 ~ 3.3 V or 1.8 V
Description
Wide range I/O. In the TCC76x, there are 2 versions of voltage condition. One is same as that of the TCC72x and the other is for low-power consumption so it has lower voltage condition than the former one. In the TCC72x this pin is contained in VDDI group. In the TCC76x, it is dedicated for oscillator power for XIN and XTIN pins, so in case of lowering VDDI than 1.8V, it should be maintained at 1.8V. The voltage level of XIN and XTIN pins must not exceed VDD_OSC level. Lower than the TCC72x The lower limit is not yet confirmed. In the TCC72x this pin is represented as VDDI_aip. Its function is same except of voltage condition. In the TCC76x, there are 2 versions of voltage condition. One is same as that of the TCC72x and the other is for low-power consumption so it has lower voltage condition than the former one. Same as the TCC72x but the lower limit below 1.8V will be determined later. Lower than the TCC72x. It has higher condition than the TCC72x.
VDD_OSC
X
TBD ~1.8 V
VDDI VDDI_ADC HPVDD VDDB_WF AVDD VDDC_WF VDDA_PLL VDDA_ADC
1.8 ~ 2.5 V 1.8 ~ 2.5 V
TBD ~ 1.8 V TBD ~ 1.8 V 2.7 ~ 3.3 V or 1.8 V TBD ~ 3.3 V TBD ~ 1.8 V TBD ~ 3.3 V
2.7 ~ 3.3 V 1.8 ~ 3.3 V 2.5 V 2.5 V
Note:
Lower limits for the voltage range under 1.8V are to be determined.
Preliminary
25-1
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TCC76X VS. TCC72X
The following tables list the pins changed from the TCC72x. The other power/ground pins not listed in the tables may have different voltage ranges from the TCC72x. Refer to Table 25.2 for those power pins.
Table 25.3 Pin Comparison - TCC760
Pin #
71 87 88 89 90 91 92 93 94 95 96
TCC720
VDDI VDDI_aip VSSI_aip VDDA_cdc LCH_OUT RCH_OUT RCH_IN MIC_IN LCH_IN VREF_cdc VSSA_cdc
TCC760
VDD_OSC VDDI_ADC VSSI_ADC PKG1 GPIO_D15 GPIO_D16 GPIO_D17 GPIO_D18 GPIO_D19 GPIO_D20 GPIO_D21
Description
Dedicated 1.8V power for crystal oscillator I/O (XIN/XOUT and XTIN/XTOUT) ADC core power. (1.8V) ADC core ground. Package ID1. PKG1 must be tied to VDD.
Internal pull-up enabled at reset. Internal pull-up enabled at reset. Internal pull-up enabled at reset. Internal pull-up enabled at reset.
Table 25.4 Pin Comparison - TCC761
Pin #
116 146 147 148 149 150 151 152 153 154 155 156
TCC721
VDDI VDDI_aip VSSI_aip VSSI_aip VDDA_cdc LCH_OUT RCH_OUT RCH_IN MIC_IN LCH_IN VREF_cdc VSSA_cdc
TCC761
VDD_OSC VDDI_ADC VSSI_ADC PKG0 PKG1 GPIO_D15 GPIO_D16 GPIO_D17 GPIO_D18 GPIO_D19 GPIO_D20 GPIO_D21
Description
Dedicated 1.8V power for crystal oscillator I/O (XIN/XOUT and XTIN/XTOUT) ADC core power. (1.8V) ADC core ground. Package ID0. PKG0 must be tied to VSS. Package ID1. PKG1 must be tied to VDD.
Internal pull-up enabled at reset. Internal pull-up enabled at reset. Internal pull-up enabled at reset. Internal pull-up enabled at reset.
Table 25.5 Pin Comparison - TCC763/TCC764 Rev. 0
Ball #
M11 D12 F9 J7 A8 A9 B9
TCC723
VDDI VDDD_aip VSSD_aip VSSI ROUT HPGND LOUT
TCC763/TCC764 Rev. 0
VDD_OSC VDDI_ADC VSSI_ADC PKG1 GPIO_D15 GPIO_D16 GPIO_D17
Description
Dedicated 1.8V power for crystal oscillator I/O (XIN/XOUT and XTIN/XTOUT) ADC core power. (1.8V) ADC core ground. Package ID1. PKG1 should be tied to VDD. ("0" may work but not recommended).
Table 25.6 Pin Comparison - TCC763/TCC764 Rev. 1
Ball #
M11 D12 F9 J7 G1 A9 G2 D2 H12
TCC723
VDDI VDDD_aip VSSD_aip VSSI SCLK HPGND SDIN CSB LRCK
TCC763/TCC764 Rev. 1
VDD_OSC VDDI_ADC VSSI_ADC PKG1 GPIO_D15 GPIO_D16 GPIO_D17 GPIO_D18 GPIO_D19
Description
Dedicated 1.8V power for crystal oscillator I/O (XIN/XOUT and XTIN/XTOUT) ADC core power. (1.8V) ADC core ground. Package ID1. PKG1 should be tied to VDD. ("0" may work but not recommended). SCLK is internally connected with GPIO_A[9] SDIN is internally connected with GPIO_A[8] Internal pull-up enabled at reset. CSB is internally connected with WMODE. Internal pull-up enabled at reset. LRCK is internally connected with GPIO_B[22]
Preliminary
25-2
TCC76x
Specification Rev. 0.07
32-bit RISC Microprocessor for Digital Media Player
February 23, 2005 TCC76X VS. TCC72X
25.3 Differences in I/O Cell Characteristics
* * * *
All the digital I/O cells except XIN and XTIN have wide operating voltage range (1.65V ~ 3.6V). Programmable output buffer drive strength and pull-up resistors. Due to I/O characteristics at low voltage levels (< 1.8V), tolerarant I/O cell was not used in the TCC76x. Input voltage must not exceed VDDIO level. Crystal oscillator input pins (XIN, XTIN) are dedicated 1.8V cells. Do not apply voltage over VDD_OSC (Max. 1.95V) for these pins.
Preliminary
25-3

▲Up To Search▲

Price & Availability of TCC76

	To Download TCC76 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .